[SOLVED] VE311 Lab 4

Note:
(1) Please use A4 size papers.
(2) The lab report should be submitted online individually.
(3) Use Proteus 8.10 for simulation before the lab session. In the Proteus library, you should be able to find all the components used in the schematics. The lab report must include both the simulation and measurement results.

1. [Common-Source with NMOS Diode-Connected Load]
(a) [20%] Design and build a common-source with diode-connected load amplifier using NMOS (VN0104). Plot VOUT vs VIN . What is the voltage gain Aυ? (Hint: Perform DC sweep of 𝑉𝐼𝑁 from 0 V to 3 V. Choose a 𝑉𝐼𝑁 at which both transistors are in the saturation region. The voltage gain is the slope of the DC sweep curve at the chosen 𝑉𝐼𝑁 .) Caution: the transistors could become very hot with high drain current. Don’t touch with bare hands before they fully cool

down.

(b) [15%] Following (a), now put two common-source NMOS in parallel. Plot VOUT vs VIN again. At the VIN chosen in (a), does the voltage gain Aυ double? Briefly explain the reason. (Note: Make sure all NMOS remain in the saturation region.)

(c) [15%] Following (b), for Vin = VIN + 0.01sin(2π102 ∙ time) , plot Vout = VOUT + υout vs time. Confirm that the amplitude of υout is close to 0.01 × Aυ.

1

2. [Common-Source with PMOS Diode-Connected Load]
(a) [20%] Design and build a common-source with diode-connected load

amplifier using NMOS (VN0104) and PMOS (VP0104). Plot VOUT vs VIN. What is the voltage gain Aυ? (Hint: Perform DC sweep of 𝑉𝐼𝑁 from 0 V to 3 V. Choose a 𝑉𝐼𝑁 at which both transistors are in the saturation region. The voltage gain is the slope of the DC sweep curve at the chosen 𝑉𝐼𝑁.) Caution: the transistors could become very hot with high drain current. Don’t touch with bare hands before they fully cool down.

(b) [15%] Following (a), now put two PMOS diode-connected loads in parallel. Plot VOUT vs VIN again. At the VIN chosen in (a), how does the voltage gain Aυ change? Briefly explain the reason. (Note: Make sure all NMOS and PMOS remain in the saturation region.)

(c) [15%] Following (b), for Vin = VIN + 0.01sin(2π102 ∙ time) , plot Vout = VOUT + υout vs time. Confirm that the amplitude of υout is close to 0.01 × Aυ.

2

Supertex inc.

VN0104

N-Channel Enhancement-Mode Vertical DMOS FET

Features

• ►  Free from secondary breakdown
• ►  Low power drive requirement
• ►  Ease of paralleling
• ►  Low CISS and fast switching speeds
• ►  Excellent thermal stability
• ►  Integral source-drain diode
• ►  High input impedance and high gain

  Applications

• ►  Motor controls
• ►  Converters
• ►  Amplifiers
• ►  Switches
• ►  Power supply circuits
• ►  Drivers (relays, hammers, solenoids, lamps,

  memories, displays, bipolar transistors, etc.)

  Ordering Information

General Description

This enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon- gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown.

Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired.

For packaged products, -G indicates package is RoHS compliant (‘Green’). Devices in Wafer / Die form are RoHS compliant (‘Green’). Refer to Die Specification VF15 for layout and dimensions.

Product Summary

Absolute Maximum Ratings

Pin Configuration

DRAIN SOURCE

GATE

TO-92 (N3)

Product Marking

YY = Year Sealed WW = Week Sealed

= “Green” Packaging

Package may or may not include the following marks: Si or

TO-92 (N3)

Drain-to-gate voltage
Operating and storage temperature

BVDGS -55OC to +150OC

SiVN 0104 YYWW

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com

Thermal Characteristics

Notes:

† ID (continuous) is limited by max rated Tj .

Electrical Characteristics (TA = 25OC unless otherwise specified)

VN0104

VGS(th) Gate threshold voltage IGSS Gate body leakage

ID(ON) On-state drain current

0.8 – 2.4 V – – 100 nA

0.5 1.0 – A 2.0 2.5 –

– 0.70 1.0 %/OC – 55 65

– 20 25 pF

– 5.0 8.0

– 1.2 1.8 V

VGS = VDS, ID= 1.0mA VGS = ± 20V, VDS = 0V

VGS = 5.0V, VDS = 25V VGS = 10V, VDS = 25V

VGS = 10V, ID = 1.0A

VGS = 0V, VDS = 25V, f = 1.0MHz

VGS = 0V, ISD = 1.0A

ΔRDS(ON)

Change in RDS(ON) with temperature

CISS Input capacitance
COSS Common source output capacitance CRSS Reverse transfer capacitance

VSD Diode forward voltage drop

Notes:

1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300μs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

VDD RL

D.U.T.

10V

INPUT
0V 10%

VDD OUTPUT

0V

90%

t(OFF) td(OFF) tf

Pulse Generator

OUTPUT

t(ON) td(ON)

10%

tr

RGEN INPUT

10% 90% 90%

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 2

3-Lead TO-92 Package Outline (N3)

VN0104

Seating Plane

D

L

b e1

e

Front View

A

c

Side View

E11 3

E 2

Bottom View

Symbol

A

b

c

D

E

E1

e

e1

L

Dimensions (inches)

NOM – – – – – – – – –

MIN

.170

.014†

.014†

.175

.125

.080

.095

.045

.500

JEDEC Registration TO-92.
* This dimension is not specified in the JEDEC drawing. † This dimension differs from the JEDEC drawing. Drawings not to scale.
Supertex Doc.#: DSPD-3TO92N3, Version E041009.

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)

1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com

Doc.# DSFP-VN0104 B071411

5

123

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Microchip:
VN0104N3-P014-G VN0104N3-P014 VN0104N3-P013 VN0104N3-P003 VN0104N3-P002 VN0104N3-G

VN0104N3 VN0104N3-P013-G VN0104N3-P002-G VN0104N3-P003-G VN0104N3-G P002 VN0104N3-G P013 VN0104N3-G P005 VN0104N3-G P003 VN0104N3-G P014 VN0104N3-G-P013

Supertex inc.

VP0104

P-Channel Enhancement-Mode Vertical DMOS FETs

Features

• ►  Free from secondary breakdown
• ►  Low power drive requirement
• ►  Ease of paralleling
• ►  Low CISS and fast switching speeds
• ►  High input impedance and high gain
• ►  Excellent thermal stability
• ►  Integral source-to-drain diode

  Applications

• ►  Motor controls
• ►  Converters
• ►  Amplifiers
• ►  Switches
• ►  Power supply circuits
• ►  Drivers (relays, hammers, solenoids, lamps,

  memories, displays, bipolar transistors, etc.)

  Ordering Information

General Description

The Supertex VP0104 is an enhancement-mode (normally- off) transistor that utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors, and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown.

Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired.

For packaged products, -G indicates package is RoHS compliant (‘Green’). Devices in Wafer / Die form are RoHS compliant (‘Green’). Refer to Die Specification VF15 for layout and dimensions.

Product Summary

Absolute Maximum Ratings

Drain-to-gate voltage

BVDGS

Pin Configuration

DRAIN SOURCE

GATE

TO-92 (N3)

Product Marking

YY = Year Sealed WW = Week Sealed

= “Green” Packaging

Package may or may not include the following marks: Si or

TO-92 (N3)

SiVP 0104 YYWW

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com

Thermal Characteristics

Notes:

† ID (continuous) is limited by max rated Tj .

Electrical Characteristics (TA = 25°C unless otherwise specified)

VP0104

VGS(th) Gate threshold voltage IGSS Gate body leakage current

ID(ON) On-state drain current

-1.5 – -3.5 V – -1.0 -100 nA

-0.15 -0.25 – A -0.5 -1.2 –

– 0.55 1.0 %/OC – 45 60

– 22 30 pF

– 3.0 8.0

– -1.2 -2.0 V

VGS = VDS, ID = -1.0mA VGS = ±20V, VDS = 0V

VGS = -5.0V, VDS = -25V VGS = -10V, VDS = -25V

VGS = -10V, ID = -500mA

VGS = 0V, VDS = -25V, f = 1.0MHz

VGS = 0V, ISD = -1.0A

ΔRDS(ON)

Change in RDS(ON) with temperature

CISS Input capacitance
COSS Common source output capacitance CRSS Reverse transfer capacitance

VSD

Notes:

Diode forward voltage drop

1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300μs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.

Switching Waveforms and Test Circuit

0V

10%

Pulse Generator

INPUT

0V

OUTPUT
VDD

RGEN INPUT

-10V
td(ON)

90%

t(OFF) td(OFF)

90% 90%

t(ON)

10%

tr

tf

D.U.T.

Output

10%

RL VDD

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 2

3-Lead TO-92 Package Outline (N3)

VP0104

Seating Plane

D

L

b e1

e

Front View

A

c

Side View

E11 3

E 2

Bottom View

Symbol

A

b

c

D

E

E1

e

e1

L

Dimensions (inches)

NOM – – – – – – – – –

MIN

.170

.014†

.014†

.175

.125

.080

.095

.045

.500

JEDEC Registration TO-92.
* This dimension is not specified in the JEDEC drawing. † This dimension differs from the JEDEC drawing. Drawings not to scale.
Supertex Doc.#: DSPD-3TO92N3, Version E041009.

(The package drawing (s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)

Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com

Doc.# DSFP-VP0104 B062211

5

123

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Microchip:
VP0104N3-G VP0104N3-P002-G VP0104N3-P014-G VP0104N3-P013-G VP0104N3-P003-G VP0104N3-P002

VP0104N3-P003 VP0104N3-P013 VP0104N3-P014 VP0104N3 VP0104N3-G P002 VP0104N3-G P005 VP0104N3- G P014 VP0104N3-G P003 VP0104N3-G P013