Note:
(1) Please use A4 size papers.
(2) Please use the SPICE model in page 3 for simulation and calculation.
1. [Common-Source with Resistive Load + Source Follower] (a)[50%]Assumeλ=0andγ=0.ForVDD =5V,VIN =1V,Vb =1V,
(Wdrawn/Ldrawn)1 = 50 μm / 2 μm, (Wdrawn/Ldrawn)2 = (Wdrawn/Ldrawn)3 = 20 μm/2μm,RD =10kΩandRL =2kΩ,whatisthevoltagegainAv for
each circuit below? Does the voltage gain drop significantly after adding a small resistive load (RL) and then recover after adding a source follower (M2 and M3) as a buffer?
(b) [25%] For each circuit below, using the design and biasing condition in (a), plot Vout and Av as a function of Vin (from 0 V to 5 V) in Pspice. Compare the hand-calculation results in (a) with the simulation results here.
(c) [25%] For circuit (iii), using the design and biasing conditions in (a), plot Vout as a function of time (from 0 to 0.1 second) in Pspice, when Vin = 1 + A × sin(2π100t) (V) and A = 0.01 V, 0.1 V and 1 V. What do you observe when the amplitude increases?
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Vacuum permittivity (𝛜𝐨) = 𝟖. 𝟖𝟓 × 𝟏𝟎−𝟏𝟐 (F / m) Silicon oxide dielectric constant (𝛜𝐫) = 𝟑. 𝟗
