Note:
(1) Please use A4 size papers.
(2) Please use the SPICE model on page 2 for simulation and calculation.
1. [Common-Source with Resistive Load] (a)[40%]Assumeλ=0andγ=0.ForVDD =5V,Vin =0.9V+small signal, RD = 15 kΩ and Ldrawn = 2 μm, find out the value Wdrawn to obtain a voltage gain |Aυ| > 10 and VOUT (the DC biasing voltage at the output) close to 2.5 V as much as possible.
(b) [30%] Using the DC biasing condition in (a), plot VOUT as a function of VIN (from 0 V to 5 V) by DC sweep in Pspice. Compare the hand- calculation result in (a) with the simulation result here. Note: the slope of the VOUT versus VIN curve at VIN = 0.9 V is the Av.
(c) [30%] Using the DC biasing conditions in (a), plot Vout as a function of time (from 0 to 0.1 second) in Pspice, when Vin = 0.9V+B× sin(2π100t) and B = 0.01 V, 0.1 V and 1 V. What do you observe when the amplitude increases?
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Vacuum permittivity (𝛜𝐨) = 𝟖. 𝟖𝟓 × 𝟏𝟎−𝟏𝟐 (F / m) Silicon oxide dielectric constant (𝛜𝐫) = 𝟑. 𝟗
