Note:
(1) Please use A4 size papers.
(2) The lab report should be submitted online individually.
(3) Use Proteus 8.10 for simulation before the lab session. In the Proteus library, you should be able to find all the components used in the schematics. The lab report must include both the simulation and measurement results.
1. [Common-Source with Source Degeneration Amplifier]
(a) [20%] (RL = ∞) Design and build a common-source with source degeneration amplifier, which has a voltage gain Aυ > 5 , using NMOS (VN0104). Plot VOUT vs VIN. Is the voltage gain Aυ close to RD⁄RS? (Hint: First choose appropriate 𝑅𝐷 and 𝑅𝑆. Second, perform DC sweep to find out a 𝑉𝐼𝑁 at which the magnitude of slope is more than 5. At the same time, make sure the NMOS is in the saturation region. If not, change for another 𝑅𝐷 and 𝑅𝑆 , and repeat the DC
sweep again.)
(b) [15%] ( RL = ∞ ) For Vin = VIN + 0.01sin(2π102 ∙ time) , plot Vout = VOUT + υout vs time. Confirm that the amplitude of υout is equal to 0.01 × Aυ.
(c) [15%] (RL = 50 kΩ) For Vin = VIN + 0.01sin(2π102 ∙ time), plot Vout = VOUT + υout vs time. Does the amplitude of υout become smaller than 0.01 × Aυ? If so, explain the reasons. (Note: Make sure the NMOS remains in the saturation region.)
1
2
2. [Source Follower]
(a) [20%] (RL = ∞) Design and build a source follower, which has a
voltage gain Aυ > 0.5, using NMOS (VN0104). Plot VOUT vs VIN. Is the voltage gain Aυ close to unity? (Hint: First choose appropriate 𝑅𝑆 . Second, perform DC sweep to find out a 𝑉𝐼𝑁 at which the magnitude of slope is more than 0.5. Here the NMOS is always in the saturation region.)
(b) [15%] ( RL = ∞ ) For Vin = VIN + 0.05sin(2π102 ∙ time) , plot Vout = VOUT + υout vs time. Confirm that the amplitude of υout is equal to 0.05 × Aυ.
(c) [15%] ( RL = 50 kΩ ) For Vin = VIN + 0.05sin(2π102 ∙ time) , plot Vout = VOUT + υout vs time. Does the amplitude of υout still maintain around 0.05 × Aυ? If so, explain the reasons.
3
Supertex inc.
VN0104
N-Channel Enhancement-Mode Vertical DMOS FET
Features
- ► Free from secondary breakdown
- ► Low power drive requirement
- ► Ease of paralleling
- ► Low CISS and fast switching speeds
- ► Excellent thermal stability
- ► Integral source-drain diode
- ► High input impedance and high gain
Applications
- ► Motor controls
- ► Converters
- ► Amplifiers
- ► Switches
- ► Power supply circuits
- ► Drivers (relays, hammers, solenoids, lamps,
memories, displays, bipolar transistors, etc.)
Ordering Information
General Description
This enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon- gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired.
|
Device |
Package Option |
Wafer / Die Options |
||
|
TO-92 |
NW |
NJ |
ND |
|
|
VN0104 |
VN0104N3-G |
VN1504NW |
VN1504NJ |
VN1504ND |
For packaged products, -G indicates package is RoHS compliant (‘Green’). Devices in Wafer / Die form are RoHS compliant (‘Green’). Refer to Die Specification VF15 for layout and dimensions.
Product Summary
Absolute Maximum Ratings
Pin Configuration
DRAIN SOURCE
GATE
TO-92 (N3)
Product Marking
YY = Year Sealed WW = Week Sealed
= “Green” Packaging
Package may or may not include the following marks: Si or
TO-92 (N3)
|
BVDSS/BVDGS (V) |
RDS(ON) (max) (Ω) |
ID(ON) (min) (A) |
|
40 |
3.0 |
2.0 |
|
Parameter |
Value |
|
Drain-to-source voltage |
BVDSS |
Drain-to-gate voltage
Operating and storage temperature
BVDGS -55OC to +150OC
|
Gate-to-source voltage |
±20V |
SiVN 0104 YYWW
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Thermal Characteristics
Notes:
† ID (continuous) is limited by max rated Tj .
Electrical Characteristics (TA = 25OC unless otherwise specified)
VN0104
|
Package |
ID † (continuous) (mA) |
ID (pulsed) (A) |
Power Dissipation @TC = 25OC |
θjc (OC/W) |
θja (OC/W) |
IDR† (mA) |
IDRM (A) |
|
TO-92 |
350 |
2.0 |
1.0 |
125 |
170 |
350 |
2.0 |
|
Sym |
Parameter |
Min |
Typ |
Max |
Units |
Conditions |
|
BVDSS |
Drain-to-source breakdown voltage |
40 |
– |
– |
V |
VGS = 0V, ID = 1.0mA |
VGS(th) Gate threshold voltage IGSS Gate body leakage
ID(ON) On-state drain current
0.8 – 2.4 V – – 100 nA
0.5 1.0 – A 2.0 2.5 –
– 0.70 1.0 %/OC – 55 65
– 20 25 pF
– 5.0 8.0
– 1.2 1.8 V
VGS = VDS, ID= 1.0mA VGS = ± 20V, VDS = 0V
VGS = 5.0V, VDS = 25V VGS = 10V, VDS = 25V
VGS = 10V, ID = 1.0A
VGS = 0V, VDS = 25V, f = 1.0MHz
VGS = 0V, ISD = 1.0A
|
ΔVGS(th) |
Change in VGS(th) with temperature |
– |
-3.8 |
-5.5 |
mV/OC |
VGS = VDS, ID= 1.0mA |
|
IDSS |
Zero gate voltage drain current |
– |
– |
1.0 |
μA |
VGS = 0V, VDS = Max Rating |
|
– |
– |
100 |
VDS = 0.8 Max Rating, VGS = 0V, TA = 125°C |
|
RDS(ON) |
Static drain-to-source on-state resistance |
– |
3.0 |
5.0 |
Ω |
VGS = 5.0V, ID = 250mA |
|
– |
2.5 |
3.0 |
VGS = 10V, ID = 1.0A |
ΔRDS(ON)
Change in RDS(ON) with temperature
|
GFS |
Forward transductance |
300 |
450 |
– |
mmho |
VDS = 25V, ID = 500mA |
CISS Input capacitance
COSS Common source output capacitance CRSS Reverse transfer capacitance
VSD Diode forward voltage drop
Notes:
|
td(ON) |
Turn-on delay time |
– |
3.0 |
5.0 |
ns |
VDD = 25V, ID = 1.0A, RGEN = 25Ω |
|
tr |
Rise time |
– |
5.0 |
8.0 |
||
|
td(OFF) |
Turn-off delay time |
– |
6.0 |
9.0 |
||
|
tf |
Fall time |
– |
5.0 |
8.0 |
|
trr |
Reverse recovery time |
– |
400 |
– |
ns |
VGS = 0V, ISD = 1.0A |
- All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300μs pulse, 2% duty cycle.)
- All A.C. parameters sample tested.
Switching Waveforms and Test Circuit
VDD RL
D.U.T.
10V
INPUT
0V 10%
VDD OUTPUT
0V
90%
t(OFF) td(OFF) tf
Pulse Generator
OUTPUT
t(ON) td(ON)
10%
tr
RGEN INPUT
10% 90% 90%
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 2
Typical Performance Curves
2.5 Output Characteristics 2.0
1.5
1.0
0.5
VGS = 10V 9.0V
8.0V 7.0V
6.0V 5.0V
4.0V
2.5 Saturation Characteristics
2.0 9.0V
1.0
0.8
0.6
0.4
0.2
3.0V 00
0
10 20 30 40
VDS (volts)
Transconductance vs. Drain Current
3.0V 0 2.0 4.0 6.0 8.0 10
VDS (volts)
2.0 Power Dissipation vs. Case Temperature
1.0
00 25 50 75 100 125 150
TC (OC)
1.0 Thermal Response Characteristics 0.8
VN0104
1.5
1.0
0.5
VGS = 10V
8.0V 7.0V
6.0V
5.0V
4.0V
|
TO-92 |
|||||
|
VDS = 25V |
|||||||||||
|
TA = -55OC |
|||||||||||
|
25 |
OC |
||||||||||
|
125OC |
|||||||||||
00 0.2 0.4 0.6 0.8 1.0
10
1.0
0.1
0.01 0.1
ID (amperes)
Maximum Rated Safe Operating Area
|
TO-92 |
||||
|
TO-92 (DC) |
||||||||||||||
|
TC = 25OC |
||||||||||||||
1.0
10 100
0.6
0.4
0.2
0
0.001 0.01
0.1 1.0 10
tP (seconds)
VDS (volts)
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 3
ID (amperes) GFS (siemens) ID (amperes)
Thermal Resistance (normalized) PD (watts) ID (amperes)
Typical Performance Curves (cont.) BVDSS Variation with Temperature
1.1
1.0
0.9
-50 0 50 100 150 Tj (OC)
2.5 Transfer Characteristics 2.0
1.5
1.0
0.5
00 2 4 6 8 10 VGS (volts)
Capacitance vs. Drain-to-Source Voltage
100
75
50
25
00 10 20 30 40 VDS (volts)
5.0 On-Resistance vs. Drain Current 4.0
3.0
2.0
1.0
00 0.5 1.0 1.5 2.0 2.5 ID (amperes)
1.6V(th) and RDS Variation with Temperature1.9
VN0104
|
VGS = 5.0V |
||||||||||||
|
VGS = 10V |
||||||||||||
VDS = 25V
TA = -55OC
25OC
125OC
|
RDS @ 10V, 1.0A |
||||||||||||
|
V(th) @ 1.0mA |
||||||||||||
|
RDS @ 5.0V, 0.25A |
||||||||||||
1.4
1.2
1.0
0.8
1.6 1.3 1.0 0.7 0.4
0.6-50 0 50 100 150 Tj (OC)
Gate Drive Dynamic Characteristics
10
8
6
4
2
00 0.2 0.4 0.6 0.8 1.0 QG (nanocoulombs)
|
f = 1.0MHz |
|||
|
CISS |
|||
|
COSS CRSS |
|
VDS = 10V |
||||||||||
|
40V |
||||||||||
|
80 pF |
||||||||||
|
40 pF |
||||||||||
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 4
C (picofarads) ID (amperes) BVDSS (normalized)
VGS (volts) VGS(th) (normalized) RDS(ON) (Ω)
RDS(ON) (normalized)
3-Lead TO-92 Package Outline (N3)
VN0104
Seating Plane
D
L
b e1
e
Front View
A
c
Side View
E11 3
E 2
Bottom View
Symbol
A
b
c
D
E
E1
e
e1
L
Dimensions (inches)
NOM – – – – – – – – –
MIN
.170
.014†
.014†
.175
.125
.080
.095
.045
.500
|
MAX |
.210 |
.022† |
.022† |
.205 |
.165 |
.105 |
.105 |
.055 |
.610* |
JEDEC Registration TO-92.
* This dimension is not specified in the JEDEC drawing. † This dimension differs from the JEDEC drawing. Drawings not to scale.
Supertex Doc.#: DSPD-3TO92N3, Version E041009.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com
Doc.# DSFP-VN0104 B071411
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