Description
Note: Some of the following problems are extensions to the problems you have solved in HW2. You may reuse your source codes as the basis.
Problem 1) Given the following circuit:
- After completing your logic simulation, pick any device offered in the tool list, finish logic synthesisand show the design hierarchy as it is in the netlist processed by the synthesis tools. You need to submit the screenshot of your design.
- Submit a Cell Properties Window like the following for your design.
- Submit the hierarchy window similar to the following.
- Submit a Schematic Window similar to the following
- Submit the Report of Timing Summary for your circuit. This is a text file similar to the following.
- Finish the device placement of your design. Submit the color map similar to the following:
Problem 2)
In HW2, you have translated the following C code into a Verilog code without pipelining. List your circuit implementation and its testbench.
x = 0; y = 0;
for (i=0; i < 3; i++ ){ x = x + y;
}
- Place and route your design with Xilinx Vivado. Print out its timing report. For yourplaced circuit, report its Critical path delay in ns.
- In HW2, you have pipelined your design in 1) using 3 stages. Now, place and route your pipelineddesign with the same device. Now print out its timing report and report its new critical path delay.
- For both 1) and 2) designs, and compare their hardware usage.
