# HW1 Improve HDL Code for Delay Performance Solved

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Problem 1) Given the following circuit:

• Implement with Verilog a module called JK_FF to realize the function of a JK flip-flop.
• Using the above JK_FF module and some extra loigc, implement with Verilog a module called X torealize the above circuit.
• Write a testbench and run logic simulation. Observe the output waveform. Deduce the functionalityof this circuit.
• Identify the critical path in the above logic diagram and use color to mark this path. How manycritical paths are there? Assuming the wire delay is negligiable.

Problem 2)Â  Given the following FIR circuit in Verilog code,

• Write a test bench for this code and perform logic simulation, and print out the waveform.
• Let the Vivado generate the logic diagram of your synthesized circuit. Print it out.
• Compare your Vivado output with the following diagram, are these two diagrams the same instructure?

3) For both Vivado output and the above diagram, find their throughput (bits/clock cycle), Latency (clock cycles), and Timing (Critical path delay). OF course, if these two diagrams are the same, you only need to do once.

Problem 3)Â

Use Page 7-10 of LectureÂ  3: Architecting for Speed in Digital Design as example.

1) Translate the following C code into a Verilog code without pipelining. List your circuit implementation and its testbench. Also print out the waveform for simulation.

x = 0; y = 0;

for (i=0; i < 3; i++ ){ x = x + y;

}

• For your code in 1), find its throughput (bits/clock cycle), Latency (clock cycles), andTiming (Critical path delay).
• Now, pipeline your design in 1). Use 3 stages. List your circuit implementation and its testbench. Also print out the waveform for simulation.
• For your code in 3), find its throughput (bits/clock cycle), Latency (clock cycles), andTiming (Critical path delay).
• Homework_2.zip