[SOLVED] CSE306 Asssignment 4-Pipelined Execution

Pipelined Execution

In this assignment, you have to design an 8-bit processor that supports pipelined datapath for a subset of MIPS instruction set. In this design, each instruction is divided into five stages: instruction fetch (IF), instruction decode (ID), execution and address calculation (EX), data memory access (MEM), and write back (WB). The length of the clock cycle equals the maxi- mum time to execute any single stage. Therefore, each instruction takes up to five clock cycles to be executed. The main components of the processor are as follows: instruction memory, data memory, register file, ALU, control unit, five pipeline registers, and a forwarding unit. Ad- ditional components such as comparators, adders, mux etc can be added as required by your design.

1 DESIGN SPECIFICATION

• Addressbusanddatabusaremultiplexed.
• Eachofdataandaddresshasasizeof8-bits.
• An8-bitALUwillberequired,hencethename8-bitMIPS.
• Theregisterfilemustincludethefollowingtemporaryregisters:

  $zero, $t0, $t1, $t2, $t3, $t4

  Each temporary register has a size of 8-bits. The assembly code that will be provided to simulate your design will use only the above mentioned registers.

  • Pipeline registers: There registers will be used between any two stages of the instruc- tion. A pipeline register can be a single register or a collection of registers. There is no restriction on the size of the pipeline registers.

1

• The control unit should be micro-programmed. The control signals associated with the operations should be stored in a special memory (you can use a separate ROM for this purpose) units as Control Words.
• Theforwardingunitisusedtodetectdatahazardandgeneratecontrolbitstoallowdata forwarding.
• Allclocksrequiredinthecircuitmustbeprovidedfromasingleclocksource.

  2 INSTRUCTION SET DESCRIPTION

  In this assignment, we will consider only the four R-type instructions. You may choose any opcode value for the given instructions.

Instruction ID

Category

Type Instruction

Shft Amnt 4-bits

R add R sub R and

R-type Opcode Src Reg 1 Src Reg 2 Dst Reg 4-bits 4-bits 4-bits 4-bits

3 MEMORY CONSIDERATIONS

Two separate memory units should be used for instruction and data.

A
B
C
D Logic R or

Arithmetic Arithmetic Logic

The format of an R- type instruction is given below.

• InstructionMemoryisaccessedthroughan8-bitaddresswhichisstoredinan8-bitPro- gram Counter (PC) register. Each access to the instruction memory provides 20-bit (in- struction) data.
• DataMemoryisalsoaccessedthroughan8-bitaddress.

  4 HANDLING HAZARDS

  In this assignment, we will only consider data hazards can occur. More precisely, we consider data hazards that can be resolved by forwarding.
  In particular you have to detect and resolve the following hazards by using forwarding tech- niques.

  • EXHazard:occurswhenthedependentinstructisintheEXstageandthepriorinstruc- tion is in MEM stage.
  • MEM Hazard: when the dependent instruction is in the EX stage and the prior instruc- tion is in WB stage.
  • Double Data Hazard: occurs when the dependent instruction is in EX stage and it de- pends on two prior instructions, one of which, is in MEM stage, and the other is in WB stage.

2

• In the following example, inst 1 creates EX hazard for inst 2 and MEM hazard for inst 3. Moreover, inst 2 and inst 3 both create double data hazard for inst 4.

inst 1: inst 2: inst 3: inst 4:

add $t1, $t2, $t3 sub $t4, $t1, $t2 or $t4, $t1, $t3 add $t4, $t4, $t3

• Notethatnostalloperationisrequiredforyourimplementation.

5 SIMULATION AND EVALUATION

To simulate your design, an assembly code consisting only 3-5 instructions will be used. Progress of your implementation will be evaluated based on the handling of the following scenarios.

• Pipelined datapath only (60% marks): No data dependency exists among the instruc- tions.
• Pipelined datapath and Ex Hazard only (60% + 15% marks): An instruction is depen- dent on its preceding instruction.
• Pipelined datapath and MEM Hazard only (60% + 15% marks): An instruction is de- pendent on its 2nd preceding instruction.
• Pipelined datapath, EX Hazard, and MEM Hazard (60% + 15% + 15% marks): An in- struction i is dependent on its preceding instruction. Another instruction j ̸= i is de- pendent on its 2nd preceding instruction.
• Pipelineddatapath,EXHazard,MEMHazard,andDoubleDataHazard(60%+15%+ 15% + 10% marks): An instruction is dependent both on its preceding and 2nd preceding instructions.

  6 REPORT CONTENT

  Contents of the report are recommended as follows:

• Section 1: Introduction
• Section2:CompleteBlockdiagramofpipelineddatapath.
• Section3:Blockdiagramsandsizeofpipelineregisters
• Section4:Mechanismandblockdiagramofforwardingunit
• Section 5: Discussion