Description

Problem 1: Circuit loading, filtering

Design the bandpass RC filter to achieve >20dB attenuation at 1MHz and less than 0.1dB attenuation from 1 Hz to 10 kHz

1. First, ignoring loading effects, determine 3dB frequencies (f_3dB,HP and f_3db,LP) that meet the specifications.
2. With R_s = 100Ω and R_L = 10MΩ, choose R₁, R₂, C₁, and C₂ to minimize loading effects.
3. Simulate the frequency response (V_o/V_s) in Ltspice and plot it together with the ideal response in MATLAB/Python.

Problem 2: Current sources, frequency response, loading

Use the circuit and variables (no values) for the following.

1. Sketch the frequency response (magnitude and phase) V_out/I_s for Z_L → .
2. Sketch the frequency response (magnitude and phase) V_out/I_s together with the unloaded response (part a) for the two conditions
   1. Z_L = C_L
   2. Z_L = R_L
3. Sketch the transient response of V_out for I_s as a current step from 0 to I_max (Z_L → ).

Problem 3: Sampling, settling, power dissipation

The clock waveform shown above is used to drive the switch open and closed (clk = 1 → switch closed, clk = 0 → switch open). T_clk is the clock period (50% duty cycle), where T_clk = 1/f_clk. V_in = 1V, R = 100 Ω, and C = 10 pF

1. What is the maximum clock frequency, f_clk, that allows 0.1% settling precision of V_cap each period?
2. Given this clock frequency, what is the average current delivered to the capacitor?
3. Verify your answers to a) and b) using Ltspice. To do this using a DC source fo V_in, you need to use an initial condition (0V) on V_cap. Include any relevant plots in your submission.
4. Perform an AC simulation on the circuit in Ltspice (switch closed). Relate the frequency response to the settling time and include any relevant plots.