## Description

# Problem 1: Circuit loading, filtering

Design the bandpass RC filter to achieve >20dB attenuation at 1MHz and less than 0.1dB attenuation from 1 Hz to 10 kHz

- First, ignoring loading effects, determine 3dB frequencies (f
_{3dB,HP}and f_{3db,LP}) that meet the specifications. - With R
_{s}= 100ā¦ and R_{L}= 10Mā¦, choose R_{1}, R_{2}, C_{1}, and C_{2}to minimize loading effects*.* - Simulate the frequency response (V
_{o}/V_{s}) in Ltspice and plot it together with the ideal response in MATLAB/Python.

# Problem 2: Current sources, frequency response, loading

Use the circuit and variables (no values) for the following.

- Sketch the frequency response (magnitude and phase) V
_{out}*/*I_{s}*for*Z_{L}ā ļ„. - Sketch the frequency response (magnitude and phase) V
_{out}/I_{s}together with the unloaded response (part a) for the two conditions- Z
_{L}= C_{L} - Z
_{L}= R_{L}

- Z
- Sketch the transient response of
*V*_{out}for I_{s}as a current step from 0 to I_{max}(Z_{L}ā ļ„).

# Problem 3: Sampling, settling, power dissipation

The clock waveform shown above is used to drive the switch open and closed (*clk* = 1 ā switch closed, *clk* = 0 ā switch open). *T _{clk}* is the clock period (50% duty cycle), where

*T*= 1/

_{clk}*f*.

_{clk}*V*= 1V,

_{in}*R*= 100 ā¦, and

*C*= 10 pF

- What is the maximum clock frequency,
*f*, that allows 0.1% settling precision of_{clk}*V*each period?_{cap} - Given this clock frequency, what is the average current delivered to the capacitor?
- Verify your answers to a) and b) using Ltspice. To do this using a DC source fo V
_{in}, you need to use an initial condition (0V) on*V*. Include any relevant plots in your submission._{cap} - Perform an AC simulation on the circuit in Ltspice (switch closed). Relate the frequency response to the settling time and include any relevant plots.