Description

For the two amplifiers shown above, the opamp has open-loop DC gain A₀, input resistance R_in, and output resistance R_out. For the Ltspice parts, use the UniversalOpamp2 (SpiceModel level.1), with R₁ = 1k and R₂ = 10k. The default open-loop output resistance for the opamp model is 0.1. You can use the ‘DC Transfer’ analysis.

1. For the inverting and non-inverting amplifiers shown in Fig 1a and 1b, determine expressions for each of the following assuming A₀ →  (infinite open-loop gain). Provide comments on how each closed-loop parameter compares to its open-loop counterpart.
   1. Closed-loop gain (V_out/V_in).
   2. Closed-loop output resistance.
   3. Closed-loop input resistance.
2.  Repeat Part a assuming A₀ is finite. Try to develop some intuition regarding how each parameter depends on A₀ and the feedback factor . Check your answer by setting A₀ →  and comparing to your answer in Part a.
3.  Assuming the opamp has a voltage offset v_OS, what is the resulting output offset for each structure? Assume A₀ → . Check your answer in Ltspice.
4.  Assuming the opamp has input bias current I_B, what is the resulting output offset for each structure? Assume A₀ → .

Problem 2: Opamp circuit transient response

             Figure 2a. Current-input integrator                                      Figure 2b. Input current pulse

For the following, assume ideal opamp behavior.

2. ( Determine an expression for the transfer function v_out/i_in.
3.  Determine an expression for the transient response of the circuit. What is the value of v_out (in terms of R, C, i_max, and t_on) at time t = t_on?

Bonus ): Design the circuit (i.e. determine R and C) to function as an integrator, such that             v_out(t_on) = i_max/C with less than 0.1% error. Use i_max = 10µA and ensure v_out doesn’t exceed a bipolar supply voltage of 2.5V. Verify your design in Ltspice.

Problem 3. Difference amplifier

Figure 3. Difference amplifier

For the following, the opamp has a DC gain (A₀) of 100 dB and a unity-gain bandwidth (f_T) of 10MHz but is otherwise ideal (R_in =  and R_out = 0). R₁ = R₂ = R₃ = R₄ = 10k.

2.  Sketch the Bode magnitude and use the graph to approximate the 3dB bandwidth. Sketch the Bode phase plot.
3. Calculate the DC gain and 3dB bandwidth of the closed-loop transfer function v_out/(v_ip – v_im). Sketch the Bode magnitude and phase of the closed-loop transfer function.
4.  What is the resistance “looking into” each input (v_im and v_ip)?
5.  Check your answers to Parts b and c in Ltspice using the Analog Devices opamp model for the AD8691.