[SOLVED] ECE 4250/7250-Lab4-4 Bit Full Adder Implementation on Xilinx Spartan-3

ECE 4250/7250
VHDL AND PROGRAMMABLE LOGIC DEVICES
LAB #4
4 Bit Full Adder Implementation on Xilinx Spartan-3
I. Objective
The objective is to become familiar with the process of creating a project, synthesizing implementing and downloading a simple design to the NEXUS4 FPGA board by using the VIVADO Project Navigator. Mainly, you will implement a 4-‐bit full adder displayed by 2 LED displays on the board.
II. Procedure
a. Creating a project in VIVADO Project Navigator, completing and adding source codes provided in advance.
b. Synthesizing the design and viewing the RTL schematic.
c. Going through the process of translating, mapping, and placing and routing to implement the design.
d. Generating programming file and configuring the device.
e. Displaying the result on LCDs and testing the design.
III. Instructions
a. Open the six attached (.vhd) files and the (.XDC) file that you have downloaded.
b. The .XDC file is complete, and there is no need to modify it.
c. You will need to complete the syntax and some part of the VHD files. At every location where you would need to fill in with code, you will see a comment.
1. Creating a project
Open the program by clicking “Start” then “All program” then “xilinex design tools” then left click on the VIVADO 2018.2 The welcome screen will show up.(figure1).
Using quick start submenu select create project the creating new vivado project screen window will pop up to the screen.(figure2).