Description
ECE 4250/7250
VHDL AND PROGRAMMABLE LOGIC DEVICES
LAB#2
DESIGN SIMULATION USING MODELSIM II
I. Objective
This objective of this lab is to use ModelSim to create and simulate a 6-bit full
subtractor.
II. Problems
In this lab you have to design and create a 6-bit full subtractor by using 6 full
subtractors as the component. Your design should have two 6-bit inputs (A, B), a borrowin
input (Bin), a 6-bit subtract output (C) and a borrow-out output (Bout) as shown in
figure 1
III. Instructions
1. Create a new project in ModelSim. Then, develop and simulate your design in
the program. Finally, display your results in the wave window of the program at least 3
samples.
2. Add or change time delay of your full subtractor. Show the simulation, describe
the difference from the pervious simulations and explain the reason.
3. Draw a completed block diagram of your design showing both internal and
external signals.
