DIC Homework Final Exam-Image Filter Engine Solved

1 Introduction

We often use the different types of filters to extract features from an image or remove noise from an image or signal. In this exam, please implement an image filter engine, which uses 3×3 mean filter, 5×5 mean filter, 3×3 max filter, and threshold to process the image. The specification and function of IFE circuit will be described in detail in the following section.

2 Design Specifications 2.1 Block overview

2.2 I/O Interface

Name I/O
clk I 1

reset I 1 ready I 1

System clock signal. This system is synchronized with the positive edge of the clock.
Active-high asynchronous reset signal.
Grayscale image ready indication signal. When this signal is high, the grayscale image memory is already

busy

iaddr

O

O 14 I

I

O

O

O

I

prepared. IFE can start sending grayscale image address to obtain the data.

The signal for grayscale image memory address, which is used to request grayscale image pixel data.

If sel is 2, the IFE circuit will process the image with 3×3 max filter. Zero- padding has to be applied on the image to keep the size of the image unchanged. Then the padded image is convolved with 3×3 max filter to obtain result image. The function of 3×3 max filter is as follows :

Result(x, y) = max {𝑖𝑚𝑔(𝑠, 𝑡)} (𝑠,𝑡)∈𝑆𝑥𝑦

Let 𝑆𝑥𝑦 represent the set of coordinates in a rectangular subimage window of size 3𝑥3, centered at point (x, y). The arithmetic max filtering process computes the max value of the corrupted image 𝑖𝑚𝑔(𝑠, 𝑡) in the area defined by 𝑆𝑥𝑦. The value of the result image at any point (x, y) is simply the max value computed using the pixels in the region defined by 𝑆𝑥𝑦.

If sel is 3, the IFE circuit will use a threshold to segment the image. The operation is defined as follows:

If img(x, y) < 127 , 𝑅𝑒𝑠𝑢𝑙𝑡(𝑥, 𝑦) = 0; else 𝑅𝑒𝑠𝑢𝑙𝑡(𝑥,𝑦)=img(x,y);

If the image intensity is less than 127, set the new intensity as zero. Otherwise, set the new intensity as origin intensity.

After the operation is finished, the busy signal should be set to 0, and then testbench will start the verification process.

In the reading phase of result memory, the addr signal represents the memory address to read and the data_rd signal will provide the data. wen signal should be set as low. The timing diagram of result memory reading operation is shown in figure 6.

In the writing phase of result memory, the addr signal informs the memory address to be written and the data_wr signal should provide the writing data. wen signal should be set as high. The timing diagram of result memory writing operation is shown in figure 7.

3 Scoring

3.1

Functional Simulation [120%]
3.1.1 Successfully pass the testfixture_mean_3x3.v. [20%] 3.1.2 Successfully pass the testfixture_mean_5x5.v. [20%] 3.1.3 Successfully pass the testfixture_max.v. [30%]
3.1.4 Successfully pass the testfixture_threshold.v. [30%] 3.1.5 The Program can finish successfully. [20%]

Your design must iteratively access the memory and control busy signal properly to get this part of scores.

4 Submission

4.1 Submitted files
You should classify your files into two directories and compress them to .zip

format. The naming rule is final_studentID_name.zip. If your file is not named according to the naming rule, you will lose five points. Please submit the compressed file to moodle and email it to [email protected]. The title of email should be set as final_studentID_name.

*.v All of your Verilog RTL code

4.2 Report file
Please follow the spec of report. If your report does not meet the spec, you may

lose part of score. You are asked to describe which testfixture you passed. Any information that you want to tell TA can also be written in the report.

4.3 Note
Please do not modify any content of testfixture. Upload your code no matter

your design can pass or not. Otherwise, TA can’t give you any point without code.