DIC Homework 4-Median Filter Engine Solved

1 Introduction

The median filter is a non-linear digital filtering technique, which is often used to remove noise from an image or signal. Such noise reduction is a typical pre- processing step to improve the results of later processing (for example, edge detection on an image). In this homework, please implement an median filter engine (MFE), which uses median filter to convolve the image. The specification and function of MFE circuit will be described in detail in the following section.

2 Design Specifications 2.1 Block overview

2.2 I/O Interface

Name I/O
clk I 1

reset I 1 ready I 1

System clock signal. This system is synchronized with the positive edge of the clock.
Active-high asynchronous reset signal.
Grayscale image ready indication signal. When this

iaddr

O

O 14 I

I

O

O

O

The signal for grayscale image memory address, which is used to request grayscale image pixel date.

The first step of the system is to perform zero-padding on the image to avoid size-changing of the image when doing MFE operation. Then the padded image is convolved with median filter to obtain result image. After the calculation is finished, the busy signal should be set to 0, and then testbench will start the verification process.

Fig. 5 – The median filtering operation.
In the reading phase, the addr signal represents the memory address of result

memory to read and the data_rd signal will provide the data. wen signal should be set as low. The timing diagram of result memory reading operation is shown in figure 6.

In the writing phase, the addr signal informs the memory address to be written and the data_wr signal should provide the writing data. wen signal should be set as high. The timing diagram of result memory writing operation is shown in figure 7.

3 Software Verification

You need to write a program to verify your circuit. You can write your program by using C, C++ and python. The requirements and functionality of this program should be as following:

1. Be able to read any jpg image. The file path for reading has to be ./image.jpg.
2. Convert RGB image to gray scale.
3. Resize the image into 128×128.
4. Add salt and pepper noise to the image.

   (You may set the probability of the noise to 0.02.)

5. Process median filtering to the image with noise.
6. Output the image with noise and the filtered image as img.dat and golden.dat,

   respectively. The format of the output files should be the same as the img.dat and golden.dat which TA gave. The output file should be able to be read by the testbench and simulate correctly.

7. Please name your program in the format: main.c, main.cpp or main.py.

4 Scoring

4.1 Functional Simulation [40%]
All of the result should be generated correctly, and you will get the following

message in ModelSim simulation.

4.2

Gate Level Simulation [20%] 4.2.1Synthesis

Your code should be synthesizable. After it is synthesized in Quartus, a file named MFE.vo will be obtained.
4.2.2Simulation

All of the result should be generated correctly using MFE.vo, and you will get the following message in ModelSim simulation.

4.3
The performance is scored by the total logic elements, total memory bit, and

embedded multiplier 9-bit element your design used in gate-level simulation and the simulation time your design takes. The score will be decided by your ranking in all received homework. (The smaller, the better)

Scoring = (Total logic elements + total memory bit + 9*embedded multiplier 9- bit element) × (longest gate-level simulation time in ns)

4.4 Software Verification [20%]
All requirements have to be completed. TA will generate testing data with your

software program to verify your design. Please ensure your design can pass with the testing data which TA provided and the testing data generated by your software program.

Performance [20%]

5 Submission

5.1 Submitted files
You should classify your files into four directories and compress them to .zip

format. The naming rule is HW4_studentID_name.zip. If your file is not named according to the naming rule, you will lose five points.

*.v All of your Verilog RTL code

*.vo Gate-Level netlist generated by Quartus
*.sdo SDF timing information generated by Quartus

5.2 Report file
Please follow the spec of report. If your report does not meet the spec, you may

lose part of score. You are asked to describe how the circuit is designed as detailed as possible, and the flow summary result is necessary in the report. Please fill the field of total logic elements, total memory bits, and embedded multiplier 9-bit elements according to the flow summary of your synthesized design. And fill the field of gate-level simulation time according to the gate-level simulation result that Modelsim shows.

5.3 Note
In this homework, you are allowed to modify the defined CYCLE in testbench

file. End_CYCLE, which decides the maximum cycles your circuit took to complete simulation, can also be modified according to your design. Please do not modify any other content of testbench.