Description
Time allowed: 6 hours
INSTRUCTIONS: Make one submission per group in the form of a single zipped folder containing your Verilog source code files(s) and Verilog testbench(es). Name your submitted zipped folder as Assgn 5 Grp <Group no>.zip and (e.g. Assgn 5 Grp 25.zip). Inside each submitted source and testbench files, there should be a clear header describing the assignment no., problem no., semester, group no., and names of group members. Liberally comment your code to improve its comprehensibility.
Figure 1: A 4-bit LFSR circuit.
1. Linear Feedback Shift Register (LFSR) Design The objective is to design a synchronous sequential circuit using four D Flip-flops, which when loaded by an initial non-zero vector called seed, cycles through all the 15 non-zero binary combinations through its state transitions, before returning to the initial vector (the seed). Thus, this circuit can be used as a modulo-15 counter, although it does not count in exact binary sequence. The only combinational gates required are XORs. These sequential circuits are commonly termed as Linear Feedback Shift Registers (LFSRs), and have extensive use in digital circuit design and testing, communication theory, etc.
Design (using Verilog), simulate (using an appropriate Verilog testbench), and implement (on a FPGA platform supported by your CAD software tool), the 4-bit LFSR shown in Fig. 1. The four stages of the sequential circuit can be loaded by an arbitrary non-zero initialization seed by using the four multiplexers as shown in the diagram. In your testbench, verify that for an initialization seed 1111, the state transition sequence followed by this circuit is as follows: 1111 → 0111 → 0011 → 0001 → 1000 → 0100 → 0010
– 2 – CS39001
Figure 2: Sequential unsigned comparator schematic.
4. [Sequential Unsigned Comparator] Consider the task of designing a sequential circuit that can compare two unsigned integers A and B, each of which is 32-bit long. The block-level schematic is shown in Fig. 2, where in every clock cycle, the circuit serially reads one bit each of A and B from their MSB sides at its input ports a and b respectively, and performs state transition of an internal finite state machine (FSM). In every clock cycle, the contents of the registers containing A and B are left-shifted. The circuit has three output lines L, E and G, exactly one of which becomes logic-1 at the end of the session indicating the result. Thus, if A < B, then {L,E,G} = 100; if A = B, then {L,E,G} = 010; if A > B, then {L,E,G} = 001.
For simplicity, assume that the machine is in an initial all-zero (reset) state before the beginning of the session (the reset signal has not been shown in the above schematic), and the input control signal OP is at logic-0; as long as OP remains at logic-0, L = E = G = 0. At the end of the session (i.e., after the arrival of least significant bits), OP flips to logic-1, indicating the end of the operation, and that the values of L, E and G are now ready to be read.
