[SOLVED] CS39001 Assignment 7

Class

Arithmetic Logic

Shift

Memory

Branch

Instruction

Add
Comp
Add immediate
Complement Immediate
AND
XOR
Shift left logical
Shift right logical
Shift left logical variable
Shift right logical
Shift right arithmetic
Shift right arithmetic variable Load Word
Store Word
Unconditional branch
Branch Register
Branch on less than 0
Branch on flag zero
Branch on flag not zero Branch and link
Branch on Carry
Branch on No Carry

Usage

add rs,rt comp rs,rt addi rs,imm compi rs,imm and rs,rt

xor rs,rt
shll rs, sh
shrl rs, sh shllv rs, rt shrl rs, rt
shra rs, sh shrav rs, rt
lw rt,imm(rs) sw rt,imm,(rs) b L

br rs bltz rs,L bz rs,L bnz rs,L bl L

bcy L bncy L

Meaning

Date: 22/10/21

rs ← (rs) + (rt)
rs ← 2’s Complement (rs)
rs ← (rs) + imm
rs ← 2’s Complement (imm)
rs ← (rs) ∧ (rt)
rs ← (rs) ⊕ (rt)
rs ← (rs) left-shifted by sh
rs ← (rs) right-shifted by sh
rs ← (rs) left-shifted by (rt)
rs ← (rs) right-shifted by (rt)
rs ← (rs) arithmetic right-shifted by sh rs ← (rs) right-shifted by (rt)
rt ← mem[(rs) + imm]
mem[(rs) + imm] ← (rt)
goto L
goto (rs)
if(rs) < 0 then goto L
if (rs) = 0 then goto L
if(rs) ̸= 0 then goto L
goto L; 31 ← (PC)+4
goto L if Carry = 1
goto L if Carry = 0

Our processor KGP-RISC has the above Instruction Set Architecture (ISA). Assume that the processor has a 32 bit word, with all the registers and memory elements having 32 bit data. The address line of the memory is also 32 bits.

We are to develop first the op-code format for the above instruction set, identify the data path element and design the data path along with the control signals. Subsequently, we shall first develop a single-cycle instruction execution unit for KGP-RISC.

Proceed step-by-step as follows:

1. For the above Instruction set, evolve a suitable instruction format. Clearly specify the fields of the opcode and mention how each of the above instruc- tions are to be encoded. Keep in mind, while deciding the op-code, you should keep provisions for adding more instructions to the ISA.
2. Identify the Data path elements and draw an architecture for the Arith- metic Logic Unit. Clearly differentiate between the data lines and control lines in your architecture diagram.1

3. Draw the complete data path along with the control signals for a single cycle execution unit for the above ISA.
4. Write the truth table for the controller signals as a function of the opcode and the function code in the instruction format. Note that for a single cycle implementation of the controller there is no state and the design is purely combinational.
5. Develop the complete RTL Verilog code for the processor. Your design should have separate and modular codes for the data-path and control- path.As an indicative guideline, your submission should consist of the following verilog files:

   (a) KGPRISC.v (b) datapath.v (c) controller.v

   (d) registerfile.v
   (e) ALU.v
   (f) InstructionMemory.v (g) DataMemory.v

   Note these are indicative names of the modules, and you can make alter- ations as you deem necessary. You can also add to it depending on the architecture you need for supporting the ISA of KGPRISC.

6. Please write suitable test-benches for verifying these components, either individually or few modules together. What is mandatory is the top-level testbench file. Your testbench should correspond to an assembly level program for your favorite algorithm. For example, you can choose to im- plement Computegcd, or SortNumbers, etc. The input to these algorithms can be numbers stored in the data-memory, and accessed by appropriate instructions by your processor.

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