[SOLVED] VLSI-Design Assignment 1

1. Install NGSPICE. Run the given net-lists (in tutorial) and observe the results (No need to sub- mit this part).
2. Plot ID vs VGS for 1.8μ NMOS transistor and estimate its VT from the graph for the following 0.18μ

   cases :

   (a) VDS =50mVandVGS issweptfrom0to1.8Vinastepof0.1V
   (b) VDS =1.8VandVGS issweptfrom0to1.8Vinastepof0.1V
   (c) Do you observe any difference in VT values in case (a) and (b) ? If yes, explain why.

3. From the simple MOS models discussed in class, find out the technology parameter μCox and VT for NMOS and PMOS devices with the help of simulations for i) Body to source voltage (VBS ) of 0V , ii) VBS = 900mV and ii) VBS = −900mV . Do you observe any difference in VT for the three cases? Explain.
4. Plot ID − VDS for the two cases shown in figures 1(a) and (b). Explain why a W/2L transistor does not behave in exactly the same way as a series combination of two W/L transistors for small values of L.

+− VDS + VGS

− = 1.8V (a)

+ VGS
− = 1.8V

(b)

= 1.8u/0.36u

ID

1. M1  W/L
   = 1.8u/0.18u
2. M2  W/L
   = 1.8u/0.18u

   Figure 1

+− VDS ID

M1
W/2L

5. Consider the circuits shown in figures 2(a) and (b). Find the peak ION and average IOF F for W= 1.8μm, W= 3.6μm, W= 18μm, W= 36μm. (Give plot snapshots and a table of ION and IOFF fordifferentW.)DoION andIOFF scalelinearlywithrespecttoW,comment.

6. Consider the schematic shown in figure 3. Switch ‘SW’ is closed at time t=0.
(a) Replace the switch ‘SW’ by an NMOS (W/L = 1.8μ ) and plot v(out), when i) vc(0−) = 0V

0.18μ
and v(in) = 1.8V, ii) vc(0−) = 1.8V and v(in) = 0V. Do you get exact same voltage at

output as at input in steady state for both the cases. Comment for both the cases with reasons for difference (if any).

ION
MN (L = 0.18 μm)

V = 1.8V +
−GS DS−−GS DS−

+ V = 1.8V

+ V = 0V

V = 1.8V +

(a)

(b)

Figure 2

v(in)−

Figure 3

(b) Replace the switch ‘SW’ by an PMOS (W/L = 1.8μ ) and plot v(out), when i) vc(0−) = 0V 0.18μ

and v(in) = 1.8V, ii) vc(0−) = 1.8V and v(in) = 0V. Do you get exact same voltage at output as at input in steady state for both the cases. Comment for both the cases with reasons for difference (if any).

(Hint : use .ic v(node-name)=value to set initial condition at a node before .control in your netlist)

7. Write a netlist for the circuit shown in figure 4. Remember to specify the AS, AD and PS, PD parameters for the transistors. Plot Vout with respect to time and calculate the propagation delay

t=0
+ SW +

v(out) C -vC

IOFF
MN (L = 0.18 μm)

a

1.8V MP

MN

1.8V MP

b c

Figure 4

MP : WP/L Vout MN : WN/L

CL L = 0.18 μm λ = 0.18 μm

Vin +−

MN

between input and output (tpd) and tabulate them for the following cases: Given: Vin (vin a 0 pulse 0 1.8 0ns 100ps 100ps 9.9ns 20ns)

1. (a)  CL =100fF,Wn =1.8μmWp =2.5×Wn
2. (b)  CL =500fFWn =1.8μmWp =2.5×Wn
3. (c)  CL =500fFWn =9μmWp =2.5×Wn.
4. (d)  From the delay table, comment how the scaling up of transistor widths affects the propa- gation delays.

Note: Delay = (rise-time + fall-time)/2, where rise-time is defined as the delay between rising output and corresponding falling input when both are at their 50% values. Similarly fall-time is defined as the delay between falling output and corresponding rising input when both are at their 50% values.

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