Ve370  Introduction to Computer Organization  Homework 2 Solution

Description

1. (5 points) Following memory location has address 0x0F000000 and content 0x15C78933.

0               1               2               3

33

89

C7

15

0x0F000000

Write RISC-V assembly instructions to load the byte C7 as a signed number into register x20, then show the content of x20 after the operations.

 

 

2. (10 points) The RISC-V assembly program below computes the factorial of a given input n (n!). The integer input is passed through register x12, and the result is returned in register x10. In the assembly code below, there are a few errors. Correct the errors.
3. (10 points) Consider a proposed new instruction named rpt. This instruction combines a loop’s condition check and counter decrement into a single instruction. For example, rpt x29, loop  would do the following:

 

• (5 points) If this instruction were to be added to the RISC-V instruction set, what is the most appropriate instruction format?

 

• (5 points) What is the shortest sequence of RISC-V instructions that performs the same operation?

4. (7 points) Given a 32-bit RISC-V machine instruction:

1_111 111_1 0110 _1010 0_001 _1010_ 1_110 0011

• (6 points) What does the assembly instruction do?

 

• (1 point) What type of instruction is it?

5. (6 points) Given RISC-V assembly instruction:
   • (5 points) What is the corresponding binary representation?

 

• (1 point) What type of instruction is it?

 

6. (12 points) If the RISC-V processor is modified to have 128 registers rather than 32 registers:
   • (4 points) show the bit fields of an R-type format instruction assuming opcode and func fields are not changed.

 

 

• (4 points) What would happen to the I-type instruction if we want to keep the total number of bits for an instruction unchanged?

 

• (4 points) What is the impact on the range of addresses for a beq instruction? Assume all instructions remain 32 bits long and the size of opcode and func fields don’t change.

 

 

7. (15 points) Convert the following assembly code fragment into machine code, assuming the memory location of the first instruction (LOOP) is 0x1000F400

 

8. (15 points) Model the Register File component shown below in Verilog HDL. Show source code and screen shots of simulation results.

 

 

9. (20 points) Model the following Immediate Generator component in Verilog HDL. Show source code, and simulation results of one instruction for each type involving immediate numbers.