[SOLVED] VE270 Assignment 4-Design of a Counter

Objectives

• To understand and design a special FSM – Counter.
• To design the counter by HDL modeling
• To experience the development process of an FPGA based digital device using HDL.
• 2. Requirement

In this lab, you are to design a device commonly used in modern computers, a 4-bit up/down synchronous binary counter. The counter is defined as follows:

• A 4-bit binary counter uses 4 flip-flop outputs to represent a binary number. It is capable of counting from 0 to 15.
• A synchronous counter implies that all flip-flops are sharing the same clock signal.
• An up/down counter is capable of counting up (incrementing) or down (decrementing).

The counter has two 1-bit control inputs called “Up/Down” and “Reset”. The counter is to increment if “Up/Down” is 1 and decrement if “Up/Down” is 0. When “Reset” is 1 the counter should go to 0 no matter what the other inputs might be. “Up/Down” input can be provided with a toggle switch. The “Reset” input can be provided with a push button. Another input to the counter is “Clock”. Rising edges of “Clock” should trigger increment or decrement of the counter.

Model the 4-bit up/down synchronous binary counter with Verilog HDL.

The outputs of the counter should be captured with 4 LEDs on the FPGA board, and also supplied to an SSD Driver modeled with Verilog HDL so that the binary number is displayed in its hexadecimal equivalent.

NOTE: the “Clock” signal can be connected to a push button or any other regular input source directly. Thus, each button press produces a rising edge.

3. Setting up Xilinx Vivado

In this section, you will set up the Xilinx Vivado digital system development environment and get it ready for circuit simulation and implementation.

• Click on the icon to open the Vivado software.
• Click “Create Project” in the left side panel shown below or from the drop down menu: File à New Project;

• Follow the navigator to choose project file location and project name;

• Select “RTL Project” option in the Project Type window, and Next;

You could check “Do not specify sources at this time” box if you want to add source file later.

• Add Sources (skip for now)
• Add Constrains (skip for now)
• Choose Default Part. There are two ways to choose parts, select by Parts or by Boards: a. Select by Parts:

Search and Choose parts: XC7A35TCPG236-1

1. Select by Boards:
   1. Download Digilent Vivado boards file from com.
   2. Copy folders in “new/board_files” into “vivado install location/Vivado/version/data/boards/board_files”. For detail, please refer to the instruction on Digilent website.

• You will find board file for Basys3

• Finish

Now a new project is created in the Vivado software.

• Find “Sources” window and click “+” to add or create source;

• Choose “Add or create design sources”; Next;

• Click “Create File”
• Choose “File type” to be Verilog, enter File name.

• Click “OK” and “Finish”; then a “Define Module” window will pop up. You can skip this step, or you can also name your module ports here;
• Write Verilog code in the file to implement your design;

Repeat steps 9) to 14) to create multiple source files;