Create a shift register custom IP as AXI-lite IP, create an RTL project and write an SDK test application code to test the IP.
Schematic
Fig. 1 M-stage Shift Register
Code
Below shows the entity and architecture of the shift register. Include the design into the project using Add Source.
entity sh_reg is generic(N: natural; — N-bit input
M: natural);– M stages
port( x : in std_logic_vector(N-1 downto 0);
z : out std_logic_vector(N-1 downto 0);
ck, en, sync: in std_logic);
end sh_reg;
architecture Behavioral of sh_reg is
