Design a circuit with reset that computes the square root of an integer. There is one input, i.e., i_radicand with 10 bits, and there is one output o_root with 5 bits. Note that both radicand and root are unsigned integers(小數點後無條件捨去). The relation between inputs and outputs is
𝑟𝑜𝑜𝑡 = 𝑓𝑙𝑜𝑜𝑟 (𝑎𝑏𝑠(√𝑟𝑎𝑑𝑖𝑐𝑎𝑛𝑑)).
Note that the two output signals: “o_root [4:0]” and “o_finish” must be registered, i.e., they are outputs of DFFs (use module FD2 (positive edge) in lib.v ).
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A possible architecture is as follows (not the best design):
Timing Diagram
Since a design can either be recursive or pipelined, the testbench provides two input strategies, i.e., recursive and pipeline.
1. Recursive
In the recursive input strategy, the circuit would be reset before every new radicand is input. Note that the radicand would be input at the next cycle right after reset.
2. Pipeline
In the pipeline input strategy, the circuit would only be reset once. After reset, a new radicand would be input every cycle. Also, o_finsh should maintain high once it was pulled up, and the order of input radicands and their corresponding roots should not be changed (First in, first out.).
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Signals Description
|
Signal name |
I/O |
Width |
Simple description |
clk rst_n i_radicand o_root o_finsih number
Input 1 Input 1 Input 10
Output 5 Output 1 Output 51
Clock signal.
Active low asynchronous reset. Radicand number.
The square root of the radicand. Indicate that the calculation was finished. The number of transistors.
Design Rules
Those who do not design according to the following rules will not be graded.
➢ LUT-based designs are not allowed.
- ➢ There should be a reset signal for the register.
- ➢ You are free to add pipeline registers.
- ➢ You can loosen your simulation timing first, (i.e., `define CYCLE XXXX in
the testbench.v), then shorten the clock period to find your critical path.
- ➢ Your design should be based on the standard cells in the lib.v. All logic operations in your design MUST consist of the standard cells instead of using
the operands such as “+”, “-”, “&”, “|”, “>”, and “<”.
- ➢ Design your homework in the given “sqrt.v” file. You are NOT ALLOWED to
change the filename and the header of the top module (i.e. the module name
and the I/O ports).
➢ If your design contains more than one module, don’t create a new file for them,just put those modules in “sqrt.v.”
Grading Policy
1. Gate-level design using Verilog (70%)
Your score will depend on both the correctness and performance of your design.
(a) Correctness Score (40%)
At this stage, we will only evaluate whether the function of the sqrt module is correct. Time and area are not considered. We provide a testbench with 1000 patterns which automatically grades your design. Your score in this part will be
40 × 𝑐𝑜𝑟𝑟𝑒𝑐𝑡 𝑛𝑢𝑚𝑏𝑒𝑟. 1000
(b) Performance Score (30%)
At this stage, you need to add up the number of transistors of all used cells in the sqrt module and connect it to number [50:0].
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Only in this section, you are allowed to use “assign” and “+” to help with calculations.
We will rank all students who pass (a) and have no connection errors on number [50:0] port. There will be a ranking according to A*T, where A represents the number of transistors and T represents the total execution time. Your performance score will be according to your ranking as the table below.
|
Percentage of passing students |
Performance Score |
If your ranking > 80% ~ 90% 70% ~ 80% 60% ~ 70% 50% ~ 60% 40% ~ 50% 30% ~ 40% 20% ~ 30% 10% ~ 20%
0% ~ 10%
90 % 30 27 24 21 18 15 12
2. Report
(a) Simulation
Write down your minimum cycle time and which strategy you used. If you do not provide these information, “1. Gate-level design using Verilog (70%)” will not get any score. This minimum cycle time would be verified by TAs. Also, put the screenshot of the summary provided by the testbench in the report.
(b) Circuit diagram
You are encouraged to use software to help draw architecture instead of hand drawing. Plot it hierarchically so that readers can understand your design easily. All of the above will improve your report score.
(5%) Plot the gate-level circuit diagram of your design.
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(c)
Discussion
Discuss your design.
➢ (3%) Introduce your design.
➢ (2%) How do you cut your pipeline?
➢ (5%) How do you improve your critical path and the number of transistors? ➢ (5%) How do you trade-off between area and speed?
➢ (5%) Compare with other architectures you have designed (if any).
(5%) Plot critical path on the diagram above.
Notification
Following are the files you will need (available on the class website) HW4.zip includes
◼ HW4_2020.pdf: This document.
◼ HW4_tutorial_2020.pdf: Tutorial in class.
◼ sqrt.v:
Dummy design file. Program the design in this file.
The header of the top module and the declaration of the I/O ports are predefined in this file and you are not allowed to change them.
- ◼ lib.v: Standard cells.
- ◼ tb.v:
The testbench for your design.
◼ pattern/radicand.dat:
Input patterns for the testbench. Please keep the hierarchy when simulation.◼ pattern/golden.dat:
Patterns of correct answers for the testbench. Please keep the hierarchy when simulation.Submission
All students who do not submit files according to the rules will get a 20% penalty. ➢ You should upload a zip file to CEIBA, the file name is “HW4_Student ID_vx”,
vx represents the version you submitted. Ex: HW4_b07901001_v1.zip ➢ Your file must conform to the following structure.
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Testbench
1. Description
- ➢ The output waveform will be dumped to file “sqrt.fsdb”, you can use nWave to examine it.
- ➢ You can change the number of test data to debug, but the final score will still test 1000 data. (`define PATTERN 1000)
- ➢ You can enable the debug function, which will display the data sent and received.
- ➢ If you passed the simulation, you should see:
Otherwise, you would see:
You would also see the summary:
Note that the performance score is the A*T value that would be used in ranking.
2. Simulation command
(a) Recursive
> ncverilog tb.v sqrt.v lib.v > ncverilog tb.v sqrt.v lib.v
(b) Pipeline
> ncverilog tb.v sqrt.v lib.v
> ncverilog tb.v sqrt.v lib.v +access+r +define+DEBUG+PIPELINE
+access+r +access+r
+define+DEBUG
+access+r
+define+PIPELINE
