- NAND3 Simulation & Layout
For this project, you will use the Cadence Design tools to layout and characterize a simple NAND3. This project will get you familiar with Cadence and also with the simulation of the layouts that you create.
Work through the Cadence tutorial.
Layout and simulate the NAND3.
You will be designing a symmetrical NAND3 with equal tp,LH and tp,HL (measured from 50% to 50%). Please get the time difference within 5ps.
The input clock slew rate is 10ps (time for input to go from high to low, and vice versa)
Assume a 10fF of load capacitance when simulating VDD = 1V and GND=0V
- Name, student number and project title on the first page of your project report
- Just below the project title, clearly state your area (widths and lengths are measured from highest IMP layer to the lowest IMP layer), delay and area x delay [7pts]
- NAND3 layout with rulers (from Cadence) showing the dimensions of the layout, label pins and show distance between them, and (snapshot of ) DRC summary [20pts]
- Waveforms showing tpHL and tpLH measured using Cadence ADE. Show the pattern for the worst-case delay and use extracted view including all parasitics [25pts – symmetry between tpHL and tpLH matters]
- Cadence Schematic clearly showing the 12 fF of load cap has been included. [5pts] The grading will be competition based.
We are looking for the smallest AND fastest NAND3 that meet the requirements. In other words, all other things being equal, the project with the smallest product of area x delay will be deemed the best. [25pts]
- Consider the following circuit. What is the logic function for this block (Boolean expression) (3pts)
- Size the gates such that the output resistance is same as that of an inverter with NMOS W/L = 4 and PMOS W/L = 8. (5pts)
- What are the input patterns (input pattern example ABCD=0000) that give worst case tpHL and tpLH. State clearly the initial input pattern and which input(s) have to make transition in order to achieve this maximum propagation delay. (Hint: consider internal nodes and use the results of question 1). Verify your result with Cadence schematic simulations. Measure the delay using WV. Submit the schematic netlist as well as the waveform output used for measuring the worst case delay. (10pts)
- For the circuit shown in Figure 1, assume that the transmission gates are all 4λ:2λ and that the inverters driving the transmission gates have PMOS transistors that are 8λ:2λ and NMOS transistors that are 4λ:2λ, where λ = 0.1µm. The output inverter drive a 50 fF load. The output inverter is f times larger than the input inverters. Answer the following questions (15 points)