[SOLVED] ELC201B Project 2-2-Stage Op-amp Design

0. Project description:

   Design the 2-stage op-amp shown in Fig.1. to have zero systematic offset and achieve the specifications listed in table I. The amplifier is supposed to provide 80dB of gain, and consume 1mW of DC power while operating from a 3.3V supply. Design the op-amp to operate properly for a maximum input common mode voltage of 3V, and a minimum output voltage of 0.2V. You can ignore the compensation of the op-amp (Ccomp). Assume that the bias current IBIAS=100uA.

   Fig. 1: 2-stage Opamp Schematic

Include in your report the hand analysis used to design the 2-stage op-amp showing:

• how you choose the device sizes (M1-M8), bias point, gm, ro
• how did you choose the gain per stage Av1 and Av2
• Op-amp input referred thermal noise
• Op-amp CMRR (common mode rejection ratio)

  Also include plots of all the simulation results supporting the specs that were achieved and summarize them in table I, i.e. include simulations for the differential gain, CMRR, and input referred noise versus frequency.

Spec.
Differential mode gain Common mode gain CMRR
Open Loop 3dB BW Input referred noise

Supply voltage
Max Input common mode Min input common mode voltage
Max output voltage
Min output voltage

Notes:

Target 80 — >60 >500 <7

3.3 3 —

— 0.2

Sim. results

Units dB dB dB MHz nV/Hz

V V V

V V

Comment

Hint: simulate the output referred noise then divide by the differential mode gain

Table I: Op-amp specs. & simulation results

• Any quantity identified in the spec table by “—” is left for your choice
• The Simulation column on the table should be filled based on your simulation results
• For the hand analysis consider only thermal noise, and you can use the following process

  parameters: VTN=0.8 V, |VTP|=0.9 V, μnCox=120 μA/V2, μpCox=40 μA/V2, n =0.04 V-1, p=0.065V-1,

  Boltzmann constant k=1.38×10-23 J/K, T=300o K, =1.

• You can use minimum length for all the transistors (1 μm)

Setup of the NMOS and PMOS transistors:

Choose an NMOS_4T from the menu of Place→ Component (as shown below) and place it in your schematic.

Double click on the transistor and choose the tab of “Value”. This is where you can change the dimensions (W,L) of the transistor.

Click on the “Edit model” button.

Copy and paste the model of the NMOS (as shown) in the “SPICE view” Make sure to click on the “Change component” button to save changes.

If you need to place another transistor in a schematic, copy the transistor that you have just created to get the correct model and you can then change the dimensions. Repeat the same for the PMOS transistor (MOS_P_4T).

Minimum length of any transistor is 1 μm. The bulk of an NMOS device should be connected to lowest voltage (ground) and that of a PMOS device should be connected to the highest voltage (VDD).

NMOS:

+(
+ LEVEL = 3
+ TOX = 200E-10 NSUB = 1E17 GAMMA = 0.5
+ PHI = 0.7 VTO = 0.8 DELTA = 3.0
+ UO = 650 ETA = 3.0E-6 THETA = 0.1
+ KP = 120E-6 VMAX = 1E5 KAPPA = 0.3
+ RSH = 0 NFS = 1E12 TPG = 1
+ XJ = 500E-9 LD = 100E-9
+ CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10 + CJ = 400E-6 PB = 1 MJ = 0.5
+ CJSW = 300E-12 MJSW = 0.5
+)
PMOS:
+(
+ LEVEL = 3
+ TOX = 200E-10 NSUB = 1E17 GAMMA = 0.6
+ PHI = 0.7 VTO = -0.9 DELTA = 0.1
+ UO = 250 ETA = 0 THETA = 0.1
+ KP = 40E-6 VMAX = 5E4 KAPPA = 1
+ RSH = 0 NFS = 1E12 TPG = -1
+ XJ = 500E-9 LD = 100E-9
+ CGDO = 200E-12 CGSO = 200E-12 CGBO = 1E-10 + CJ = 400E-6 PB = 1 MJ = 0.5
+ CJSW = 300E-12 MJSW = 0.5
+)