Description

• Build and test a multi-cycle MIPS CPU that implements a subset of the MIPS instruction set.
• Design a microcode control unit.

Description

In this lab, you will use Logisim to build a multi-cycle CPU, to further increase your knowledge of MIPS and as an introduction to microcode control. To test your CPU, you will run assembly language programs and simulate them in Logisim. You will be provided with a base project as a starting point. Appendix D of Computer Organization and Design, available online at http://booksite.elsevier.com/9780124077263/ downloads/advance_contents_and_appendices/appendix_D.pdf, will be very useful for this lab. You can find it along with a sample program that you will be tested against in the Lab 3 assignment on SmartSite. You must implement the CPU control using microcode. The microcode implementation that you pick is up to you.

Details

In this lab, you will have a single RAM acting as both instruction and data memory. Just like Lab 2, you will have a 256 word-deep memory. You can logically reserve the first 128 words for instructions and the next 128 for data. This means that, in the programs you write and you will be tested on, the PC should not go beyond the 128th word’s address. Likewise, all memory locations accessed by LW and SW should be between the 129th and 256th words of memory. As in Lab 2, the PC is incremented by 4, so, in your instruction memory, the first instruction will be at 0x00000000, the second at 0x00000004, the third at 0x00000008, and so on.

You will be given an empty project to start your lab that includes an implementation of an ALU and a Register File. The file Lab 3 Given.circ contains these sub-circuits.

Instructions to Implement

Your CPU must execute the following instructions:

• All previous instructions from Lab 2.

– AND, ANDI, ADD, ADDI, OR, ORI, SUB, SLT, SLTU*, XOR, LW, SW, BEQ, J, JAL, JR

• SLL
• SRL

As with the previous lab, the instructions for SLTU are incorrect in the given MIPS PDF. The instructions should read:

If rs < rt with an unsigned comparison, put 1 into rd. Otherwise put 0 into rd.

For this lab, you must use microcode to implement the main control unit. The exact microcode implementation is up to you. All control signals must come from a ROM.

Subcircuits

Register File

• The register file is the same as in Lab 2.

ALU

• The ALU will now support SLL and SRL, and there is now a Shamt[4..0] (shift amount) input.
• When performing shift operations, the B input is shifted by the amount specified by Shamt.
• The control signal ALUCtl is described below:

Operation	ALUCtl3	ALUCtl2	ALUCtl1	ALUCtl0
OR	0	0	0	0
SLTU	0	0	0	1
SLT	0	0	1	0
ADD	0	0	1	1
SUB	0	1	0	0
XOR	0	1	0	1
AND	0	1	1	0
		…
SLR	1	1	1	0
SLL	1	1	1	1