PROBLEM 1.1:
Write the truth table for the following gates:
(a) AND (b) OR
(c) NOR
(d) NAND (e) XOR (f) XNOR
PROBLEM 1.2:
Define De Morgan’s law and show how it would be used to simplify the following Boolean equation.
Y =A+AB+AB+A+B (1)
PROBLEM 1.3:
Given the following Truth Table that represents a 16QAM signal.
I Q -3 -3 -3 -1 -3 1 -3 3 -1 -3 -1 -1 -1 1 -1 3
Symbol I Q Symbol 0000 1-3 1100 0001 1-1 1101 0011 11 1111 0010 13 1110 0100 3-3 1000 0101 3-1 1001 0111 31 1011 0110 33 1010
Find:
- (a) The Boolean Equation for each bit of the Symbol using a Karnaugh Map.
- (b) Create a schematic of digital gates to represent the Boolean Equation. Label each gate and each wire.
- (c) Implement the schematic in Verilog using Altera’s Schematic Entry tool
- (d) Program the schematic in Verilog using a text based tool.
