Description
In this lab, you will use the Quartus II software package to design and test combinational circuit designs with multiplexers and decoders. You will learn standard IC chips 74151, an 8-to-1 multiplexer, and 74154, a 4-to-16 decoder and use them to implement logic functions. The requirements for this lab consist of completing Quartus II designs and printing any necessary schematic diagrams, performing functional simulations, testing the designs on DE1 board, and submitting a laboratory report.
Lab procedures
Design A. Implement Design A from the preplab in Quartus II and perform functional simulations. Test all input valuations.
Download and test Design A to the DE1 board, Cyclone® V 5CSEMA5F31C6 chip.
Suggested pin assignment:
SW0 to SW2 for x,y and z
SW9 for the enable input
LEDR0 and LEDR1 for f and 𝑓𝑓. ̅
Based on your tests in Quartus II and with DE1, fill out the following truth table.
| f | |||||
| x | y | z | expected | Quartus II | DE1 |
| 0 | 0 | 0 | |||
| 0 | 0 | 1 | |||
| 0 | 1 | 0 | |||
| 0 | 1 | 1 | |||
| 1 | 0 | 0 | |||
| 1 | 0 | 1 | |||
| 1 | 1 | 0 | |||
| 1 | 1 | 1 |
Design B. Implement Design B from the preplab in Quartus II and perform functional simulations. Test all input valuations.
Download and test Design B to the DE1 board, Cyclone® V 5CSEMA5F31C6 chip.
Suggested pin assignment:
SW0 to SW3 for x0 to x3
SW8 and SW9 for two enable inputs LEDR0 and LEDR1 for f1 and f2
Based on your tests in Quartus II and with DE1, fill out the following truth table.
| N1 | N2 | expected | Quartus II | DE1 | |||||
| x3 | x2 | x1 | x0 | f1 | f0 | f1 | f0 | f1 | f0 |
| 0 | 0 | 0 | 0 | ||||||
| 0 | 0 | 0 | 1 | ||||||
| 0 | 0 | 1 | 0 | ||||||
| 0 | 0 | 1 | 1 | ||||||
| 0 | 1 | 0 | 0 | ||||||
| 0 | 1 | 0 | 1 | ||||||
| 0 | 1 | 1 | 0 | ||||||
| 0 | 1 | 1 | 1 | ||||||
| 1 | 0 | 0 | 0 | ||||||
| 1 | 0 | 0 | 1 | ||||||
| 1 | 0 | 1 | 0 | ||||||
| 1 | 0 | 1 | 1 | ||||||
| 1 | 1 | 0 | 0 | ||||||
| 1 | 1 | 0 | 1 | ||||||
| 1 | 1 | 1 | 0 | ||||||
| 1 | 1 | 1 | 1 | ||||||
Q1 : Implement a 2-out-of-4 detector using the 4-to-1 multiplex. You need to draw the schematics of your design.
Q2 : Implement the following logic function using a 2-to-1 multiplexer via Shannon’s Expansion (expansion over one variable). You need to show your immediate steps.
𝒇𝒇 = 𝒙𝒙̄𝟏𝟏⨁𝒙𝒙𝟐𝟐 + 𝒙𝒙̄𝟏𝟏𝒙𝒙̄𝟑𝟑
Q3 : Implementation of the following logic function
𝒇𝒇(𝒘𝒘𝟏𝟏, 𝒘𝒘𝟐𝟐, 𝒘𝒘𝟑𝟑) = 𝒎𝒎(𝟎𝟎, 𝟐𝟐, 𝟑𝟑, 𝟒𝟒, 𝟓𝟓, 𝟕𝟕)
using a 4-to-1 multiplexer. Please use Shannon’s Expansion (expansion over two variables). You need to show your immediate steps.
Q4 . Implementation of the following logic function using 3-to-8 binary decoder and some necessary gates: 𝑓𝑓(𝑥𝑥, 𝑦𝑦, 𝑧𝑧) = 𝑥𝑥⨁𝑧𝑧 + 𝑦𝑦𝑧𝑧.
