Description

This is an exercise in designing combinational circuits that can perform binary-to-decimal number conversion and binary-coded-decimal (BCD) addition.

Preparation marks for this lab: 1 mark for verilog code for each of Parts I through IV. Also, 1 mark in total for simulation results of just Parts II and III.

In-Lab marks: 2 marks for Part III, 3 marks Part IV. One bonus mark is available for Part V.

Part I

We wish to display on the 7-segment displays HEX1 and HEX0 the values set by the switches SW₇₋₀. Let the values denoted by SW₇₋₄ and SW₃₋₀ be displayed on HEX1 and HEX0, respectively. Your circuit should be able to display the digits from 0 to 9, and should treat the valuations 1010 to 1111 as don’t-cares.

1. Create a new project which will be used to implement the desired circuit on the Altera DE1-SoC board. Theintent of this exercise is to manually derive the logic functions needed for the 7-segment displays. Therefore, you should use only simple Verilog assign statements in your code and specify each logic function as a Boolean expression.
2. Write a Verilog file that provides the necessary functionality. Include this file in your project and assign thepins on the FPGA to connect to the switches and 7-segment displays. Make sure to include the necessary pin assignments.
3. Compile the project and download the compiled circuit into the FPGA chip.
4. Test the functionality of your design by toggling the switches and observing the displays.

Part II

You are to design a circuit that converts a four-bit binary number V = v₃v₂v₁v₀ into its two-digit decimal equivalent D = d₁d₀. Table 1 shows the required output values. A partial design of this circuit is given in Figure 1. It includes a comparator that checks when the value of V is greater than 9, and uses the output of this comparator in the control of the 7-segment displays. You are to complete the design of this circuit.

v3v2v1v0	d1	d0
0000	0	0
0001	0	1
0010	0	2
…	…	…
1001	0	9
1010	1	0
1011	1	1
1100	1	2
1101	1	3
1110	1	4
1111	1	5

Table 1. Binary-to-decimal conversion values.

The output z for the comparator circuit can be specified using a single Boolean expression, with the four inputs V₃₋₀. Design this Boolean expression by making a truth table that shows the valuations of the inputs V₃₋₀ for which z has to be 1.

Notice that the circuit includes a 4-bit wide 2-to-1 multiplexer (a similar multiplexer was described as part of Laboratory Exercise 1). The purpose of this multiplexer is to drive digit d₀ with the value of V when z = 0, and the value of A when z = 1. To design circuit A consider the following. For the input values V ≤ 9, the circuit A does not matter, because the multiplexer in Figure 1 just selects V in these cases. But for the input values V > 9, the multiplexer will select A. Thus, A has to provide output values that properly implement Table 1 when V > 9. You need to design circuit A so that the input V = 1010 gives an output A = 0000, the input V = 1011 gives the output A = 0001, …, and the input V = 1111 gives the output A = 0101. Design circuit A by making a truth table with the inputs from V and the outputs A₃₋₀.

Perform the following steps:

1. Write Verilog code to implement your design. The code should have the 4-bit input SW₃₋₀, which should be used to provide the binary number V , and the two 7-bit outputs HEX1 and HEX0, to show the values of decimal digits d₁ and d₀. The intent of this exercise is to use simple Verilog assign statements to specify the required logic functions using Boolean expressions. Your Verilog code should not include any if-else, case, or similar statements.
2. Make a Quartus project for your Verilog module.
3. Compile the circuit and use functional simulation to verify the correct operation of your comparator, multiplexers, and circuit A.
4. Download the circuit into an FPGA board. Test the circuit by trying all possible values of V and observing the output displays.

Figure 1: Partial design of the binary-to-decimal conversion circuit.

Part III

Figure 2a shows a circuit for a full adder, which has the inputs a, b, and c_i, and produces the outputs s and c_o. Parts b and c of the figure show a circuit symbol and truth table for the full adder, which produces the two-bit binary sum c_os = a + b + c_i. Figure 2d shows how four instances of this full adder module can be used to design a circuit that adds two four-bit numbers. This type of circuit is usually called a ripple-carry adder, because of the way that the carry signals are passed from one full adder to the next. Write Verilog code that implements this circuit, as described below.

1. a) Full adder circuit b) Full adder symbol

b a ci	co
0 0 0 0 0 1 0 1 0 0    1 1 1    0 0 1 0 1 1 1 0 1 1 1	0 0 0 1 0   1 1 1 1   1

s

0

1

1

0

0

0

1. c) Full adder truth table d) Four-bit ripple-carry adder circuit

Figure 2: A ripple-carry adder circuit.

1. Create a new Quartus project for the adder circuit. Write a Verilog module for the full adder subcircuit andwrite a top-level Verilog module that instantiates four instances of this full adder.
2. Use switches SW₇₋₄ and SW₃₋₀ to represent the inputs A and B, respectively. Use SW₈ for the carry-in c_in of the adder. Connect the outputs of the adder, c_out and S, to the red lights LEDR.
3. Include the necessary pin assignments for the DE1-SoC board, compile the circuit, and download it into theFPGA chip.
4. Test your circuit by trying different values for numbers A, B, and c_in.

Part IV

In part II we discussed the conversion of binary numbers into decimal digits. For this part you are to design a circuit that has two decimal digits, X and Y , as inputs. Each decimal digit is represented as a 4-bit number. In technical literature this is referred to as the binary coded decimal (BCD) representation.

You are to design a circuit that adds the two BCD digits. The inputs to your circuit are the numbers X and Y , plus a carry-in, c_in. When these inputs are added, the result will be a 5-bit binary number. But this result is to be displayed on 7-segment displays as a two-digit BCD sum S₁S₀. For a sum equal to zero you would display S₁S₀ = 00, for a sum of one S₁S₀ = 01, for nine S₁S₀ = 09, for ten S₁S₀ = 10, and so on. Note that the inputs X and Y are assumed to be decimal digits, which means that the largest sum that needs to be handled by this circuit is S₁S₀ = 9+9+1 = 19. Perform the steps given below.

1. Create a new Quartus project for your BCD adder. You should use the four-bit adder circuit from part III toproduce a four-bit sum and carry-out for the operation X + Y .

A good way to work out the design of your circuit is to first make it handle only sums (X +Y ) ≤ 15. With these values, your circuit from Part II can be used to convert the 4-bit sum into the two decimal digits S₁S₀. Then, once this is working, modify your design to handle values of 15 < (X + Y ) ≤ 19. One way to do this is to still use your circuit from Part II, but to modify its outputs before attaching them to the 7-segment display to make the necessary adjustments when the sum from the adder exceeds 15.

Write your Verilog code using simple assign statements to specify the required logic functions–do not use other types of Verilog statements such as if-else or case statements for this part of the exercise.

2. Use switches SW₇₋₄ and SW₃₋₀ for the inputs X and Y , respectively, and use SW₈ for the carry-in. Connect the four-bit sum and carry-out produced by the operation X + Y to the red lights LEDR. Display the BCD values of X and Y on the 7-segment displays HEX5 and HEX3, and display the result S₁S₀ on HEX1 and HEX0.
3. Since your circuit handles only BCD digits, check for the cases when the input X or Y is greater than nine. If this occurs, indicate an error by turning on the red light LEDR₉.
4. Include the necessary pin assignments for the DE1-SoC board, compile the circuit, and download it into theFPGA chip.
5. Test your circuit by trying different values for numbers X, Y , and c_in.

Part V

In part IV you created Verilog code for a BCD adder. A different approach for describing the adder in Verilog code is to specify an algorithm like the one represented by the following pseudo-code:

• T₀ = A + B + c₀
• if (T₀ > 9) then
• Z₀ = 10;
• c₁ = 1;
• else
• Z₀ = 0;
• c₁ = 0;
• end if
• S₀ = T₀− Z₀
• S₁ = c₁

It is reasonably straightforward to see what circuit could be used to implement this pseudo-code. Lines 1 and 9 represent adders, lines 2-8 correspond to multiplexers, and testing for the condition T₀ > 9 requires comparators. You are to write Verilog code that corresponds to this pseudo-code. Note that you can perform addition operations in your Verilog code instead of the subtraction shown in line 9. The intent of this part of the exercise is to examine the effects of relying more on the Verilog compiler to design the circuit by using if-else statements along with the Verilog > and + operators. Perform the following steps:

1. Create a new Quartus project for your Verilog code. Use switches SW₇₋₄ and SW₃₋₀ for the inputs A and B, respectively, and use SW₈ for the carry-in. The value of A should be displayed on the 7-segment display HEX5, while B should be on HEX3. Display the BCD sum, S₁S₀, on HEX1 and HEX0.
2. Use the Quartus RTL Viewer tool to examine the circuit produced by compiling your Verilog code. Comparethe circuit to the one you designed in Part IV.
3. Download your circuit onto the DE1-SoC board and test it by trying different values for numbers A and B.