Description
- Introduction:
Booth algorithm is a multiplication operation that multiplies two numbers in two’s complement notation. The detail algorithm is described as below:
- Assume that the multiplicand m is x-bit and multiplier r is y-bit.
Initialize a register P for the final result, and the length is x+y+1 bits.
The initial value of P is 0(x bits)_r(y bits)_0(1 bit).
- The rightmost 2 bits used for the selection of different executions.
| Rightmost 2 bits | Execution |
| 00 | No execution |
| 01 | Add m to the left part of P |
| 10 | Subtract m from the left part of P |
| 11 | No execution |
* Overflow condition can be ignored during the execution.
- Arithmetically shift 1 bit on P.
- Repeat the step (2) and (3) for y times.
- The final answer is obtained by dropping the LSB from P.
- Design Specifications:
- Block Overview
Fig. 1. The block overview.
- I/O Interface
| Signal Name | I/O | width | Description |
| in1 | I | 6 | Multiplicand |
| in2 | I | 6 | Multiplier |
| out | O | 12 | Product |
- File Description
| File Name | Description |
| booth.v | The top module of the design. |
| booth_tb.v | The testbench file. The content in this file is not allowed to be modified. |
- Scoring:
- Functional Simulation [60%]
All of the result should be generated correctly, and you will get the following message in ModelSim simulation.
Fig. 2. Functional simulation result.
- Gate-Level Simulation [30%]
- Synthesis
Your code should be synthesizable. After it is synthesized in Quartus, a file named booth.vo will be obtained.
- Simulation
All of the result should be generated correctly using booth.vo, and you will get the following message in ModelSim simulation.
Fig. 3. Gate-level simulation result.
  Device：Cyclone II EP2C70F896C8
- Performance [10%]
The performance is scored by the clock width your design can operate in gatelevel simulation. The score will be decided by your ranking in all received homework. (The smaller the better)
