In this project you will design the exact same ALU as in the lecture notes. Your design will include:
- 4×1 MUX module
- 1-bit ALU
- 32-bit ALU module
1-bit ALU module will be designed same as shown below:
32-bit ALU module will be constructed using 1-bit ALU modules as shown below:
You have to write your own testbench on Verilog and show that the project is working right.
The ALU must support AND, OR, ADD, SUBTRACT and SET ON LESS THAN operations.
Write a report that explains your Verilog modules and the testbench results. You should test all operations that ALU allows. Also report how many logic gates you used for the ALU.
