# CSC 355 Digital Logic and Computer Design ASSIGNMENT 3 Solved

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1. Design a finite state machine as a clocked Mealy sequential network with one input X and one output Z. The machine is a recognizer that has an output trigger sequence and a reset output to zero sequence. If the input sequence â€˜0 1 1 0â€™ occurs then the output changes to â€˜1â€™ coincident with the last bit of the sequence. The output remains at â€˜1â€™ until the reset sequence â€˜0 1 0â€™ is received on the input and, in this case, the output changes to â€˜0â€™ coincident with the last bit of the sequence. Initially, output Z is â€˜0â€™.
For example,
X = 0 0 1 0 0 0 1 1 0 0 1 0 1 0 1 1 0 0 0 0 0 1 0 1
Z = 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1 1 1 0 0
For the design, provide a state graph, the corresponding state table and the output table. Number the states S0, S1, â€¦ Maximum marks will be given for a correct solution with the minimum number of states. Do not continue the design beyond this point. (In particular, there is no need to implement using flip-flops.)
2. The state diagram for a sequential circuit is given below:
The encoded state table for the circuit is given in Table 5-15 (4th edition) or Table 4-14 (5th edition) of your textbook.
Assuming the circuit is to be designed using two JK Flip-flops, determine the flip-flop input equations, JA, KA, JB, and KB.
3. Text (Mano, Kime, Martin, 5th edition) , page 283 #4-14 â€“ parts a) b) and c) only, or Text (Mano, Kime, 4th edition) , page 283 #5-14 â€“ parts a) b) and c) only.
AB=000
AB=010
AB=100
AB=110
XY=00 / Z=0
XY=01 / Z=0
XY=00 / Z=1
XY=01 / Z=1
XY=11 / Z=0
XY=10 / Z=0
XY=11 / Z=0
J
Q
Q
K
SET
CLR
J
Q
Q
K
SET
CLR
A
B
CK
X
4. A gated latch (G-L FF) behaves as follows:
If G = 0, the flip-flop does not change state.
If G = 1, the next state of the flip-flop is equal to the value of L,
where G and L are the two inputs to the flip flop.
Derive the characteristic (next- state) equation for the flip-flop.
5. Complete the timing diagram for the sequential circuit shown.
Z
B
A
X
CK
6. Design a static RAM memory cell, using a set-reset flip flop for the internal storage and any other devices you require, with the following features. There are two control lines, X and Y, an input line Ip, and an output line Op (there is no clock). The values of X, Y and Ip require the following actions to be taken:
ïƒ˜ X = 0, Y = 0 : the memory cell is not selected ( flip-flop contents unchanged, Op is to be in the high impedance state Z)
ïƒ˜ X = 1, Y = 1 : read the memory cell (output Op is equal to contents of flip-flop)
ïƒ˜ X = 1, Y = 0 : write to the memory cell (flip-flop contents to be equal to value on Ip, Op is to be in the high impedance state Z)
X = 0, Y = 1 : toggle the memory cell (invert the flip-flop contents, Op is to be in the high impedance state Z).
7. Text (Mano, Kime, Martin, 5th edition) , page 287 #4-23, or Text (Mano, Kime, 4th edition) , page 287 #5-22.
8. Text (Mano, Kime, Martin, 5th edition) , page 287 #4-25, or Text (Mano, Kime, 4th edition) , page 288 #5-24.
9. Text (Mano, Kime, Martin, 5th edition) , page 318 #5-1, or Text (Mano, Kime, 4th edition) , page 330 #6-1.
10. Text (Mano, Kime, Martin, 5th edition) , page 318 #5-2, or Text (Mano, Kime, 4th edition) , page 330 #6-2.
11. Text (Mano, Kime, Martin, 5th edition) , page 319 #5-4 a), or Text (Mano, Kime, 4th edition) , page 333 #6-21.
12. Text (Mano, Kime, Martin, 5th edition) , page 478 #8-1 Text (Mano, Kime, 4th edition) , page 490 #9-1
13. Text (Mano, Kime, Martin, 5th edition) , page 482 #8-17 Text (Mano, Kime, 4th edition) , page 494 #9-17
Some Karnaugh maps for your editing pleasure
A\BC
00
01
11
10
0
1
AB\CD
00
01
11
10
00
01
11
10
Change the variables if your expressions require different variable names

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