Description
Preliminary Report/Preliminary Design Report: Pipeline hazards evaluation and preparing test modules in MIPS (Due date of this part is the same for all).
Implementation and simulation of the MIPS-lite pipelined processor.
- Please drop your written Preliminary Design Report into the box provided in front of the lab by 10:40 am. No late submission!
DUE TIME OF PART 2—DIFFERENT FOR EACH SECTION:
- You have to demonstrate your Part 2 lab work to the TA for grade by 12:15 in the morning lab and by 17:15 in the afternoon lab. Your TAs may give further instructions on this. If you wait idly and show your work last minute, 20 points may be taken off from your grade.
- At the conclusion of the demo for getting your grade, you will upload your lab work to the Unilica Assignment, for similarity testing by MOSS. Please see the related section below for further instructions on MOSS submission.
Preliminary Work / Preliminary Design Report
At the end of this lab, you will have implemented the pipelined MIPS architecture that can be seen in the file that is provided as PipelineDatapath.PNG (Notice that there is no early branch prediction in this pipeline. Hence, the branch resolution is done in the Execute Decode stage.). Note also that there is no jump instruction implemented as well. Be sure to have a printout of the pipelined processor with you, to use during the lab. Your PDR should contain the following items:
- a) Cover page, with university name, department name, and course name and number at the top, “Preliminary Design Report”, Lab # (e.g. 5), Section #, and your name and ID# in the middle, and the date of your lab at the bottom.
- b) The list of all hazards that can occur in this pipeline. For each hazard, give its type (data or control), its specific name (“compute-use” “load-use”, “load-store” “J-type jump”, “branch” etc.), the pipeline stages that are affected.
- c) For each hazard, give the solution (forwarding, stalling, flushing, combination of these), and explanation of what, when, how.
- d) The logic equations for each signal output by the hazard unit, as a function of the input signals that come to the hazard unit. This hazard unit should handle all the data and control hazards that can occur in your pipeline (listed in b) so that your pipelined processor computes correctly.
- e) Write small test programs, in MIPS assembly, that will show whether the pipelined processor is working or not. Each of your test programs should be designed to catch problems, if there are any, in the execution of MIPS instructions in your pipelined machine. Write:
- A test program with no hazards (to verify that there are no problems with the connections in your pipeline etc.)
- A test program that has one type of hazard, and another, and another…
In the end, have at least 4 test programs (testing at least 3 hazards) with their machine code (in hex).
You can use the student-written assembler tool available online to help you quickly implement your test programs[1]. Remember that the goal of testing is to verify that all the instructions are fully working, and that all the instructions are working even in the presence of hazards.
Part 2: Implementation and Simulation
- a) You are given a skeleton System Verilog code for your pipelined MIPS processor in the file txt. The places in the code that needs to be modified are shown with comment blocks above them. Fill them to implement Pipelined Processor. You don’t need to follow the skeleton code point by point. If you think your design is better, you are welcome to try it in your code, as long as your version of the code works, too.
- b) Now make a System Verilog testbench file and using Xilinx Vivado, simulate your Pipeline Processor by executing the test programs you wrote at Prelim e). Implement a new top module in order to see memwrite, regwrite, writedata, pc, instruction and resultw signals. Study the results given in the simulation window. Find each instruction, and understand its values. Do this step for each of the test programs you wrote.
- c) When you have integrated all the System Verilog modules together and your whole pipelined MIPS is working in simulation with the test programs you wrote, call the TA and show it for grade. To get full points from this part, you must know and understand everything about what you have done.
