Description
1. Implement the finite state machine the next state function of which is shown in Table 1. The machine takes a two-bit input (Y[1:0]). The output function is not specified and can be ignored for this assignment. Suppose
Table 1. Next state function
Current state
S0 S1 S2 S3 S3 S3 S4 S5 S6 S7 S8 S9 S10 S10
S11
Input (Y[1:0]) 2’bxx 2’bxx 2’bxx 2’b00 2’b01 2’b1x 2’bxx 2’bxx 2’bxx 2’bxx 2’bxx 2’bxx 2’b00 2’b01, 2’b1x 2’bxx 2’bxx
Next state
S1 S2 S3 S4 S5 S6 S7 S7 S7 S8 S9 S10 S11 S12
S0
S0
a state incrementer can be used to compute the next state along with dispatch ROMs, a microcode ROM, and a
S12
state selection multiplexer. The microcode ROM takes only the current state as input to look up a row and outputs
the branch control for computing the next state (note that Y cannot be used as an input to the microcode ROM).
The ROMs should be implemented as arrays and initialized within an initial block. The current state should be displayed on each rising clock edge in your top module. Two time units before each rising clock edge a new input is sent to the FSM (note that the input is two bits), but the state change occurs on rising edges only. Model a propagation delay of two time units in the state registers. The clock should have a cycle time of ten time units with 50% duty. Simulate for ten clock cycles.
2.[60 marks] Construct a module that takes as input four three-bit values treated as unsigned numbers and com- putes the index of the smallest value. For example, if the inputs are 110, 010, 001, and 111, the output is 2 indicating that the input at position two is the smallest (input index starts at zero on the left hand side and ends at three on the right hand side). Display the output index in your top module. Simulate for ten different input sets. Keep a delay of one time unit between two consecutive input sets.
