Computer System Architecture Project Solved

“Processor design is the design engineering task of creating a processor, a key component of computer hardware. The design process involves choosing an instruction set and a certain execution paradigm, and results in a microarchitecture. The mode of operation of any processor is the execution of lists of instructions. Instructions typically include those to compute or manipulate data values using registers, change or retrieve values in read/write memory, perform relational tests between data values and to control program flow.”

In this project, you will simulate a fictional processor design and architecture using Java. You are asked to choose one of four processor packages described in the upcoming sections.

Package Selection Form: https://forms.gle/7uwWNwsC9akPsdWt5
Project Selection Deadline: Wednesday 02/06/2021 at 11:59 pm
Note: The processor package choice is based on a first come, first served basis (each package has a maximum capacity of 25 teams).

Project Instructions

Please read the following instructions carefully:

1. a)  Any case of plagiarism will result in a zero.
2. b)  Any case of cheating will result in a zero.
3. c)  A cheating detection tool will be used to compare the submitted projects against all online and offline implementations similar to the project idea.• The projects that have more than 50% similarity percentage will receive a zero.
4. d)  It is your responsibility to ensure that you have:• Submitted before the deadline.
   • Submitted the correct file(s).
   • Submitted the correct file(s) names.
5. e)  The project deadline is on Saturday 26/06/2021 at 11:59 pm.

1

1 Package 1: Fillet-O-Neumann with logical shifts on the side 1.1 Memory Architecture

a) Architecture: Von Neumann

• Von Neumann Architecture is a digital computer architecture whose design is based on the concept of stored program computers where program data and instruction data are stored in the same memory.

b) Memory Size: 2048 * 32

Main Memory
32 Bits / Row

Data (1024 to 2047) Instructions (0 to 1023)

2048 Rows

• The main memory addresses are from 0 to 211 − 1 (0 to 2047).
• Each memory block (row) contains 1 word which is 32 bits (4 bytes). • The main memory is word addressable.
• Addresses from 0 to 1023 contain the program instructions.
• Addresses from 1024 to 2048 contain the data.

c) Registers: 33

• Size: 32 bits
• 31 General-Purpose Registers (GPRS)

– Names: R1 to R31 • 1 Zero Register

– Name: R0

– Hard-wired value “0” (cannot be overwritten by any instruction). • 1 Program Counter

• –  Name: PC
• –  A program counter is a register in a computer processor that contains the address (loca-tion) of the instruction being executed at the current time.
• –  As each instruction gets fetched, the program counter is incremented to point to the nextinstruction to be executed.

1.2 Instruction Set Architecture

a) Instruction Size: 32 bits b) Instruction Types: 3

R-Format
OPCODE R1 R2 R3 SHAMT

4 5 5 5 13

I-Format
OPCODE R1 R2 IMMEDIATE

4 5 5 18 2

J-Format OPCODE ADDRESS 4 28

c) Instruction Count: 12
• The opcodes are from 0 to 11 according to the instructions order in the following table:

Name

Mnemonic Type

Format

ADD R1 R2 R3 SUB R1 R2 R3 MULI R1 R2 IMM ADDI R1 R2 IMM

BNE R1 R2 IMM

ANDI R1 R2 IMM ORI R1 R2 IMM
J ADDRESS
SLL R1 R2 SHAMT SRL R1 R2 SHAMT LW R1 R2 IMM

SW R1 R2 IMM

Operation

R1 = R2 + R3
R1 = R2 – R3
R1 = R2 * IMM
R1 = R2 + IMM IF(R1 != R2) {
PC = PC+1+IMM } R1 = R2 & IMM

R1 = R2 | IMM
PC = PC[31:28] || ADDRESS R1 = R2 << SHAMT
R1 = R2 >>> SHAMT
R1 = MEM[R2 + IMM] MEM[R2 + IMM] = R1

Add ADD Subtract SUB Multiply Immediate MULI Add Immediate ADDI

Branch if Not Equal BNE

And Immediate ANDI Or Immediate ORI Jump J Shift Left Logical∗ SLL Shift Right Logical∗ SRL Load Word LW Store Word SW

R R I I

I

I I J R R I I

∗ SLL and SRL: R3 will be 0 in the instruction format.
“||” symbol indicates concatenation (0100 || 1100 = 01001100).

1.3 Datapath

a) Stages: 5

• All instructions regardless of their type must pass through all 5 stages even if they do not needto access a particular stage.
• Instruction Fetch (IF): Fetches the next instruction from the main memory using the address in the PC (Program Counter).
• Instruction Decode (ID): Decodes the instruction and reads any operands required from the register file.
• Execute (EX): Executes the instruction. In fact, all ALU operations are done in this stage.
• Memory (MEM): Performs any memory access required by the current instruction. For loads, it would load an operand from the main memory, while for stores, it would store an operand into the main memory.
• Write Back (WB): For instructions that have a result (a destination register), the Write Back writes this result back to the register file.b) Pipeline: 4 instructions (maximum) running in parallel
  • Instruction Fetch (IF) and Memory (MEM) can not be done in parallel since they accessthe same physical memory.
  • At a given clock cycle, you can either have the IF, ID, EX, WB stages active, or the ID,EX, MEM, WB stages active.
  • Number of clock cycles: 7 + ((n − 1) ∗ 2), where n = number of instructions– Imagine a program with 7 instructions: ∗ 7+(6∗2)=19clockcycles

    – You are required to understand the pattern in the example and implement it. 3

Package 1 Pipeline

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Cycle 11 Cycle 12 Cycle 13 Cycle 14 Cycle 15 Cycle 16 Cycle 17 Cycle 18 Cycle 19

Instruction Decode (ID)

Instruction 1 Instruction 1 Instruction 2 Instruction 2 Instruction 3 Instruction 3 Instruction 4 Instruction 4 Instruction 5 Instruction 5 Instruction 6 Instruction 6 Instruction 7 Instruction 7

Execute (EX)

Instruction 1 Instruction 1

Memory (MEM)

Instruction Instruction Instruction Instruction Instruction Instruction Instruction

Write Back (WB)

1 2 3 4 5 6 7

Instruction Fetch (IF) Instruction 1

Instruction 2 Instruction 3 Instruction 4 Instruction 5 Instruction 6 Instruction 7

The pattern is as follows:

Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction

2
2
3
3
4
4
5
5
6
6
7
7

Instruction 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5 Instruction 6 Instruction 7

2

2.1

Package 2: Double Big Harvard combo large circular shifts Memory Architecture

•

• –  You fetch an instruction
• –  An instruction stays in the Decode (ID) stage for 2 clock cycles.
• –  An instruction stays in the Execute (EX) stage for 2 clock cycles.
• –  An instruction stays in the Memory (MEM) stage for 1 clock cycle.
• –  An instruction stays in the Write Back (WB) stage for 1 clock cycle.
• –  You can not have the Instruction Fetch (IF) and Memory (MEM) stages working in par-allel. Only one of them is active at a given clock cycle.

every 2 clock

cycles starting from

clock cycle 1.

a) Architecture: Harvard

• Harvard Architecture is the digital computer architecture whose design is based on the concept where there are separate storage and separate buses (signal path) for instruction and data. It was basically developed to overcome the bottleneck of Von Neumann Architecture.

b) Instruction Memory Size: 1024 * 16
Instruction Memory

16 Bits / Row Rows

• The instruction memory addresses are from 0 to 210 − 1 (0 to 1023). • Each memory block (row) contains 1 word which is 16 bits (2 bytes).

1024

4

• The instruction memory is word addressable.
• The program instructions are stored in the instruction memory.

c) Data Memory Size: 2048 * 8

Data Memory
8 Bits / Row

2048 Rows

• The data memory addresses are from 0 to 211 − 1 (0 to 2047).
• Each memory block (row) contains 1 word which is 8 bits (1 byte). • The data memory is word/byte addressable (1 word = 1 byte).
• The data is stored in the data memory.

d) Registers: 66

• Size: 8 bits
• 64 General-Purpose Registers (GPRS)

– Names: R0 to R63 • 1 Status Register

76543210

000CVNSZ

– Name: SREG
– A status register, flag register, or condition code register (CCR) is a collection of status

flag bits for a processor.
– The status register has 5 flags updated after the execution of specific instructions:

• ∗  Carry Flag (C): Indicates when an arithmetic carry or borrow has been generated out of the most significant bit position.· C = 1 if result > Byte.MAX_VALUE
  · C = 0 if result <= Byte.MAX_VALUE
  · Full cases and scenarios explanation:
• ∗  Two’s Complement Overflow Flag (V): Indicates when the result of a signed number operation is too large, causing the high-order bit to overflow into the sign bit.
  • ·  If 2 numbers are added, and they both have the same sign (both positive or both negative), then overflow occurs (V = 1) if and only if the result has the opposite sign. Overflow never occurs when adding operands with different signs.
  • ·  If 2 numbers are subtracted, and their signs are different, then overflow occurs (V = 1) if and only if the result has the same sign as the subtrahend.
  • ·  The difference between carry and overflow is explained in: https://piazza.com/ class/kmoutjsotl76h5?cid=79
• ∗  Negative Flag (N): Indicates a negative result in an arithmetic or logic operation. · N = 1 if result is negative.
  · N = 0 if result is positive or zero.
• ∗  Sign Flag (S): Indicates the expected sign of the result (not the actual sign).
  · S = N ⊕ V (XORing the negative and overflow flags will calculate the sign flag).
• ∗  Zero Flag (Z): Indicates that the result of an arithmetic or logical operation was zero. · Z=1ifresultis0.

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· Z=0ifresultisnot0.
∗ Since all registers are 8 bits, and we are only using 5 bits in the Status Register for

the flags, you are required to keep Bits7:5 cleared “0” at all times in the register. • 1 Program Counter

• –  Name: PC
• –  Type: Special-purpose register with a size of 16 bits (not 8 bits).
• –  A program counter is a register in a computer processor that contains the address (loca-tion) of the instruction being executed at the current time.
• –  As each instruction gets fetched, the program counter is incremented to point to the nextinstruction to be executed.

2.2 Instruction Set Architecture

a) Instruction Size: 16 bits b) Instruction Types: 2

R-Format OPCODE R1 R2

466

I-Format
OPCODE R1 IMMEDIATE

466

c) Instruction Count: 12
• The opcodes are from 0 to 11 according to the instructions order in the following table:

Name

Mnemonic Type

Format

ADD R1 R2 SUB R1 R2 MULI R1 R2 LDI R1 IMM

BEQZ R1 IMM

AND R1 R2 ORR1R2 JRR1R2
SLC R1 IMM SRC R1 IMM
LB R1 ADDRESS SB R1 ADDRESS

Operation

R1 = R1 + R2
R1 = R1 – R2
R1 = R1 * R2
R1 = IMM
IF(R1 == 0) {
PC = PC+1+IMM } R1 = R1 & R2

R1 = R1 | R2
PC = R1 || R2
R1 = R1 << IMM | R1 >>> 8 – IMM R1 = R1 >>> IMM | R1 << 8 – IMM R1 = MEM[ADDRESS] MEM[ADDRESS] = R1

Add ADD Subtract SUB Multiply MUL Load Immediate LDI

Branch if Equal Zero BEQZ

And AND Or OR Jump Register JR Shift Left Circular SLC Shift Right Circular SRC Load Byte LB Store Byte SB

R R R I

I

R R R I I I I

“||” symbol indicates concatenation (0100 || 1100 = 01001100).

d) The Status Register (SREG) flags are affected by the following instructions:

• The Carry flag (C) is updated every ADD, SUB, and MUL instruction.
• The Overflow flag (V) is updated every ADD and SUB instruction.
• The Negative flag (N) is updated every ADD, SUB, MUL, AND, OR, SLC, and SRC instruc- tion.

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• The Sign flag (S) is updated every ADD and SUB instruction.
• The Zero flag (Z) is updated every ADD, SUB, MUL, AND, OR, SLC, and SRC instruction. • A flag value can only be updated by the instructions related to it.

2.3 Datapath

a) Stages: 3

• All instructions regardless of their type must pass through all 3 stages.
• Instruction Fetch (IF): Fetches the next instruction from the main memory using the address in the PC (Program Counter).
• Instruction Decode (ID): Decodes the instruction and reads any operands required from the register file.
• Execute (EX): Executes the instruction. In fact, all ALU operations are done in this stage. Moreover, it performs any memory access required by the current instruction. For loads, it would load an operand from the main memory, while for stores, it would store an operand into the main memory. Finally, for instructions that have a result (a destination register), it writes this result back to the register file.b) Pipeline: 3 instructions (maximum) running in parallel

• Number of clock cycles: 3 + ((n − 1) ∗ 1), where n = number of instructions – Imagine a program with 7 instructions:

∗ 3+(6∗1)=9clockcycles
– You are required to understand the pattern in the example and implement it.

Package 2 Pipeline

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9

Instruction Fetch (IF) Instruction 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5 Instruction 6 Instruction 7

Instruction Decode (ID)

Instruction 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5 Instruction 6 Instruction 7

Execute (EX)

Instruction 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5 Instruction 6 Instruction 7

3

3.1

Package 3: Spicy Von Neumann Fillet with extra moves Memory Architecture

a) Architecture: Von Neumann

• Von Neumann Architecture is a digital computer architecture whose design is based on the concept of stored program computers where program data and instruction data are stored in the same memory.

b) Memory Size: 2048 * 32

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Main Memory
32 Bits / Row

Data (1024 to 2047) Instructions (0 to 1023)

• The main memory addresses are from 0 to 211 − 1 (0 to 2047).
• Each memory block (row) contains 1 word which is 32 bits (4 bytes). • The main memory is word addressable.
• Addresses from 0 to 1023 contain the program instructions.
• Addresses from 1024 to 2048 contain the data.

c) Registers: 33

• Size: 32 bits
• 31 General-Purpose Registers (GPRS)

– Names: R1 to R31 • 1 Zero Register

– Name: R0

– Hard-wired value “0” (cannot be overwritten by any instruction). • 1 Program Counter

• –  Name: PC
• –  A program counter is a register in a computer processor that contains the address (loca-tion) of the instruction being executed at the current time.
• –  As each instruction gets fetched, the program counter is incremented to point to the nextinstruction to be executed.

3.2 Instruction Set Architecture

a) Instruction Size: 32 bits b) Instruction Types: 3

R-Format
OPCODE R1 R2 R3 SHAMT

4 5 5 5 13

I-Format
OPCODE R1 R2 IMMEDIATE

4 5 5 18

J-Format OPCODE ADDRESS 4 28

c) Instruction Count: 12
• The opcodes are from 0 to 11 according to the instructions order in the following table:

2048 Rows

8

Name Mnemonic Type

Format

ADDR1R2R3 SUBR1R2R3 MULR1R2R3 MOVI R1 IMM

JEQ R1 R2 IMM

ANDR1R2R3 XORI R1 R2 IMM JMP ADDRESS LSL R1 R2 SHAMT LSR R1 R2 SHAMT MOVR R1 R2 IMM MOVM R1 R2 IMM

Operation

R1 = R2 + R3
R1 = R2 – R3
R1 = R2 * R3
R1 = IMM
IF(R1 == R2) {
PC = PC+1+IMM } R1 = R2 & R3

R1 = R2 ⊕ IMM
PC = PC[31:28] || ADDRESS R1 = R2 << SHAMT
R1 = R2 >>> SHAMT
R1 = MEM[R2 + IMM] MEM[R2 + IMM] = R1

Add ADD Subtract SUB Multiply MUL Move Immediate∗ MOVI

Jump if Equal JEQ

And AND Exclusive Or Immediate XORI Jump JMP Logical Shift Left∗∗ LSL Logical Shift Right∗∗ LSR Move to Register MOVR Move to Memory MOVM

R R R I

I

R I J R R I I

∗ MOVI: R2 will be 0 in the instruction format.
∗∗ LSL and LSR: R3 will be 0 in the instruction format.
“||” symbol indicates concatenation (0100 || 1100 = 01001100).

3.3 Datapath

1. a)  Stages: 5
   • All instructions regardless of their type must pass through all 5 stages even if they do not needto access a particular stage.
   • Instruction Fetch (IF): Fetches the next instruction from the main memory using the address in the PC (Program Counter).
   • Instruction Decode (ID): Decodes the instruction and reads any operands required from the register file.
   • Execute (EX): Executes the instruction. In fact, all ALU operations are done in this stage.
   • Memory (MEM): Performs any memory access required by the current instruction. For loads, it would load an operand from the main memory, while for stores, it would store an operand into the main memory.
   • Write Back (WB): For instructions that have a result (a destination register), the Write Back writes this result back to the register file.
2. b)  Pipeline: 4 instructions (maximum) running in parallel
   • Instruction Fetch (IF) and Memory (MEM) can not be done in parallel since they accessthe same physical memory.
   • At a given clock cycle, you can either have the IF, ID, EX, WB stages active, or the ID,EX, MEM, WB stages active.
   • Number of clock cycles: 7 + ((n − 1) ∗ 2), where n = number of instructions– Imagine a program with 7 instructions: ∗ 7+(6∗2)=19clockcycles

     – You are required to understand the pattern in the example and implement it.

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Package 3 Pipeline

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Cycle 11 Cycle 12 Cycle 13 Cycle 14 Cycle 15 Cycle 16 Cycle 17 Cycle 18 Cycle 19

Instruction Decode (ID)

Instruction 1 Instruction 1 Instruction 2 Instruction 2 Instruction 3 Instruction 3 Instruction 4 Instruction 4 Instruction 5 Instruction 5 Instruction 6 Instruction 6 Instruction 7 Instruction 7

Execute (EX)

Instruction 1 Instruction 1

Memory (MEM)

Instruction Instruction Instruction Instruction Instruction Instruction Instruction

Write Back (WB)

1 2 3 4 5 6 7

Instruction Fetch (IF) Instruction 1

Instruction 2 Instruction 3 Instruction 4 Instruction 5 Instruction 6 Instruction 7

The pattern is as follows:

Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction Instruction

2
2
3
3
4
4
5
5
6
6
7
7

Instruction 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5 Instruction 6 Instruction 7

4

4.1

Package 4: Double McHarvard with cheese arithmetic shifts Memory Architecture

•

• –  You fetch an instruction
• –  An instruction stays in the Decode (ID) stage for 2 clock cycles.
• –  An instruction stays in the Execute (EX) stage for 2 clock cycles.
• –  An instruction stays in the Memory (MEM) stage for 1 clock cycle.
• –  An instruction stays in the Write Back (WB) stage for 1 clock cycle.
• –  You can not have the Instruction Fetch (IF) and Memory (MEM) stages working in par-allel. Only one of them is active at a given clock cycle.

every 2 clock

cycles starting from

clock cycle 1.

a) Architecture: Harvard

• Harvard Architecture is the digital computer architecture whose design is based on the concept where there are separate storage and separate buses (signal path) for instruction and data. It was basically developed to overcome the bottleneck of Von Neumann Architecture.

b) Instruction Memory Size: 1024 * 16
Instruction Memory

16 Bits / Row Rows

• The instruction memory addresses are from 0 to 210 − 1 (0 to 1023). • Each memory block (row) contains 1 word which is 16 bits (2 bytes).

1024

10

• The instruction memory is word addressable.
• The program instructions are stored in the instruction memory.

c) Data Memory Size: 2048 * 8

Data Memory
8 Bits / Row

2048 Rows

• The data memory addresses are from 0 to 211 − 1 (0 to 2047).
• Each memory block (row) contains 1 word which is 8 bits (1 byte). • The data memory is word/byte addressable (1 word = 1 byte).
• The data is stored in the data memory.

d) Registers: 66

• Size: 8 bits
• 64 General-Purpose Registers (GPRS)

– Names: R0 to R63 • 1 Status Register

76543210

000CVNSZ

– Name: SREG
– A status register, flag register, or condition code register (CCR) is a collection of status

flag bits for a processor.
– The status register has 5 flags updated after the execution of specific instructions:

• ∗  Carry Flag (C): Indicates when an arithmetic carry or borrow has been generated out of the most significant bit position.
  • ·  C = 1 if result > Byte.MAX_VALUE
  • ·  C = 0 if result <= Byte.MAX_VALUE
  • ·  Full cases and scenarios explanation: https://piazza.com/class/kmoutjsotl76h5?cid=295
• ∗  Two’s Complement Overflow Flag (V): Indicates when the result of a signed number operation is too large, causing the high-order bit to overflow into the sign bit.
  • ·  If 2 numbers are added, and they both have the same sign (both positive or both negative), then overflow occurs (V = 1) if and only if the result has the opposite sign. Overflow never occurs when adding operands with different signs.
  • ·  If 2 numbers are subtracted, and their signs are different, then overflow occurs (V = 1) if and only if the result has the same sign as the subtrahend.
  • ·  The difference between carry and overflow is explained in: https://piazza.com/ class/kmoutjsotl76h5?cid=79
• ∗  Negative Flag (N): Indicates a negative result in an arithmetic or logic operation. · N = 1 if result is negative.
  · N = 0 if result is positive or zero.
• ∗  Sign Flag (S): Indicates the expected sign of the result (not the actual sign).
  · S = N ⊕ V (XORing the negative and overflow flags will calculate the sign flag).
• ∗  Zero Flag (Z): Indicates that the result of an arithmetic or logical operation was zero. 11

· Z=1ifresultis0.

· Z=0ifresultisnot0.
∗ Since all registers are 8 bits, and we are only using 5 bits in the Status Register for

the flags, you are required to keep Bits7:5 cleared “0” at all times in the register. • 1 Program Counter

• –  Name: PC
• –  Type: Special-purpose register with a size of 16 bits (not 8 bits).
• –  A program counter is a register in a computer processor that contains the address (loca-tion) of the instruction being executed at the current time.
• –  As each instruction gets fetched, the program counter is incremented to point to the nextinstruction to be executed.

4.2 Instruction Set Architecture

a) Instruction Size: 16 bits b) Instruction Types: 2

R-Format OPCODE R1 R2

466

I-Format
OPCODE R1 IMMEDIATE

466

c) Instruction Count: 12
• The opcodes are from 0 to 11 according to the instructions order in the following table:

Name

Mnemonic Type

Format

ADD R1 R2 SUB R1 R2 MULI R1 R2 MOVI R1 IMM

BEQZ R1 IMM

ANDI R1 IMM EOR R1 R2 BRR1R2
SAL R1 IMM
SAR R1 IMM
LDR R1 ADDRESS STR R1 ADDRESS

Operation

R1 = R1 + R2
R1 = R1 – R2
R1 = R1 * R2
R1 = IMM
IF(R1 == 0) {
PC = PC+1+IMM } R1 = R1 & IMM

R1 = R1 ⊕ R2
PC = R1 || R2
R1∗ = R1[7-IMM:0]] || 0 R1∗∗ = R1[7] || R1[7:IMM] R1 = MEM[ADDRESS] MEM[ADDRESS] = R1

Add ADD Subtract SUB Multiply MUL Move Immediate MOVI

Branch if Equal Zero BEQZ

And Immediate ANDI Exclusive Or EOR Branch Register BR Shift Arithmetic Left SAL Shift Arithmetic Right SAR Load to Register LDR Store from Register STR

R R R I

I

I R R I I I I

“||” symbol indicates concatenation (0100 || 1100 = 01001100).
∗ 0 is repeated IMM times before right concatenating it to R1[7-IMM:0]. ∗∗ R1[7] is repeated IMM times before left concatenating it to R1[7:IMM].

d) The Status Register (SREG) flags are affected by the following instructions:

• The Carry flag (C) is updated every ADD, SUB, and MUL instruction. • The Overflow flag (V) is updated every ADD and SUB instruction.

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• The Negative flag (N) is updated every ADD, SUB, MUL, ANDI, EOR, SAL, and SAR instruction.
• The Sign flag (S) is updated every ADD and SUB instruction.
• The Zero flag (Z) is updated every ADD, SUB, MUL, ANDI, EOR, SAL, and SAR instruction.
• A flag value can only be updated by the instructions related to it.4.3 Datapath

  a) Stages: 3

• All instructions regardless of their type must pass through all 3 stages.
• Instruction Fetch (IF): Fetches the next instruction from the main memory using the address in the PC (Program Counter).
• Instruction Decode (ID): Decodes the instruction and reads any operands required from the register file.
• Execute (EX): Executes the instruction. In fact, all ALU operations are done in this stage. Moreover, it performs any memory access required by the current instruction. For loads, it would load an operand from the main memory, while for stores, it would store an operand into the main memory. Finally, for instructions that have a result (a destination register), it writes this result back to the register file.b) Pipeline: 3 instructions (maximum) running in parallel

  • Number of clock cycles: 3 + ((n − 1) ∗ 1), where n = number of instructions – Imagine a program with 7 instructions:

  ∗ 3+(6∗1)=9clockcycles
  – You are required to understand the pattern in the example and implement it.

Package 4 Pipeline

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9

The following guidelines

Program Flow

Instruction Fetch (IF) Instruction 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5 Instruction 6 Instruction 7

Instruction Decode (ID)

Instruction 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5 Instruction 6 Instruction 7

Execute (EX)

Instruction 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5 Instruction 6 Instruction 7

Guidelines

must followed in all packages:

a) You must write your program in assembly language in a text file.

b) Your must read the instructions from the text file, and parse them according to their types/formats (opcode and other relevant fields).

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c) You must store the parsed version of the instructions in the memory (instruction segment of main memory or instruction memory according to your package).

4. d)  You should start the execution of your pipelined implementation by fetching the first instruc- tion from the memory (instruction segment of main memory or instruction memory) at Clock Cycle 1.
5. e)  You should continue the execution based on the example provided in the Datapath section of each package reflecting the different stages working in parallel.
6. f)  The Clock Cycles can be simulated as a variable that is incremented after finishing the required stages at a given time.• Example:

   fetch (); decode (); execute (); // memory();

// writeback ();

cycles++;

Printings

The following items must be printed in the console after each Clock Cycle:

1. a)  The Clock Cycle number.
2. b)  The Pipeline stages:• Which instruction is being executed at each stage?
   • What are the input parameters/values for each stage?
3. c)  The updates occurring to the registers in case a register value was changed.
4. d)  The updates occurring in the memory (data segment of main memory or data memory according to your package) in case a value was stored or updated in the memory.
5. e)  The content of all registers after the last clock cycle.
6. f)  The full content of the memory (main memory or instruction and data memories according to yourpackage) after the last clock cycle.

Submission

You should submit a ZIP file to the course email containing the following items:

• All “.java” code files used in the project.
• Any additional library used.
• A text file containing the team number, team name, package number and name, and team members’ names, IDs, and tutorials.The ZIP file should be named in the following format: Team_[TeamNumber]_[PackageName]

  – PackageNumber = {1, 2, 3, or 4} based on the selected/assigned project.

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