COEN 316 Lab 5 – Datapath/Control Unit Integration and system testing Solved

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The datapath designed in the previous lab contains 10 control signals. The function of the control unit, which is the focus of this lab, is to produce the correct values for all the control signals at the proper point in time.  Tables 1 and 2 lists the 10 control signals and summarizes their operation.

Table 1: Single bit control signals.

Control signal value = 0 value = 1
reg_write do not write into register file write into register file
reg_dst rt is the destination register rd is the destination register
reg_in_src d_out of data_cache is the d_in to the register file ALU output is the d_in to the

register file

alu_src out_b of register file (rt) is the y input of the ALU sign extended immediate is the y input of the ALU
add_sub ALU operation = addition ALU operation = subtraction
data_write do not write into data cache write into data cache

Table 2: Two bit control signals.

Control signal value = 00 value = 01 value =10 value = 11
logic_func AND OR XOR NOR
func load upper immediate set less arithmetic logic
branch_type no branch beq bne bltz
pc_sel no jump (PC+1, or PC+target addressifbranch condition is true) jump (PC = target address) jump register (PC = rs) not used

Table 3 lists the 20 instructions implemented by the CPU together with the values of the 6 bit opcode field and the 6 bit func field (contained within the instruction as per Figure 1 of Lab 4) together with the 10 control signals.  Table 3 is partially completed, you are to complete the table by deriving the values of the 10 control signals based upon Tables 1 and 2 and knowledge of which control signals need to be activated during a particular instruction in order to achieve correct execution of the instruction. Refer to your datapath of Lab 4 to assist in completing the table.

Table 3: 20 instructions with opcode and function fields and control signals. [1]

Inst. op func reg_wr ite reg_dst reg_in


alu_src add_su b data_w rite logic_f


func branch


lui 001111   1 0 1 1 0

(don’t care)

0 00

(don’t care)

00 00 00
add 000000 100000 1 1 1 0 0 0 00 10 00 00
sub 000000 100010                    
slt 000000 101010                    
addi 001000   1 0 1 1 0 0 00 10 00 00
slti 001010                      
and 000000 100100 1 1 1 0 1 0 00 11 00 00
or 000000 100101                    
xor 000000 100110                    
nor 000000 100111                    
andi 001100                      
ori 001101                      
xori 001110                      
lw 100011   1 0 0 1 0 0 10

(don’t care)

10 00 00
sw 101011                      
j 000010                      
jr 000000 001000                    
bltz 000001                      
beq 000100   0 0 0 0 0 0 00 00 01 00
bne 000101                      

Note that Table 3 has some entries which are “don’t care” values which have arbitrarily assigned with values. Procedure

Complete Table 3 by deriving all the remaining values of the control signals. Design the control unit using VHDL. The control unit in this implementation is a combinational logic circuit whose inputs are the opcode and function fields of the instruction and the outputs are the 10 control signals.  Test your control unit (through simulation) to ensure that it generates the correct values for the 10 control signal for each of the 20 instructions. You may either use a VHDL process for the control unit which will be added to your datapath designed in Lab 4, or you may design the control unit as a separate entity and use it as an additional component to be added with a port map statement to your existing datapath. Alternatively, the datapath of Lab 4 may be added as a component together with an instance of your control unit to create a new top level entity (with name cpu).

Use the following VHDL entity specification for the final CPU design:

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_signed.all;

entity  cpu  is port(reset : in std_logic;      clk   : in std_logic;      rs_out, rt_out : out std_logic_vector(3 downto 0);     — output ports from register file

pc_out : out std_logic_vector(3 downto 0); — pc reg      overflow, zero : out std_logic); — will not be constrained                                       —  in Xilinx since                                       — not enough LEDs end cpu;

You will note that in the cpu entity, the top-level ports consist of the out_a ( rs ) and out_b (rt) ports of the register file and the PC register (with negated outputs to account for the active-low LEDs on the XUPV2Pro FPGA board.   There is an asynchronous reset (which will be constrained to a

switch input) and a clock input (constrained to the debounced clock input switch on the expansion

IO board of the FPGA board ). It is important that you use the above entity specification, as it is the one which will be used during the lab test.

Test your complete CPU by writing different test programs into the I-cache and verify correct operation of your CPU on the XUPV2Pro FPGA development board.