CA2 Homework 3 Solved

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Programming

In this homework, we will use verilog to implement simple ALU, FPU and CPU in this homework.

We use Icarus Verilog to run the simulation, and we use gtkwave to check waveform. We will score your implementations under these settings.

Folder structure for this homework:

HW3

|– ALU                                                                                            // Part 1

|               |– alu.f                                                                                   <– specify the files you use

|              ‘– codes                                                                                <– put all the *.v here

|           |                  ‘– alu.v

|               |– test_alu                                                                      <– run the test

|               |– testbench.v                                                                 <– test for corretness

|                ‘– testcases/                                                                 <– testcases

|                               ‘– generate.cpp                                               <– used to generate testcases

|– FPU                                                                                            // Part 2

|               |– fpu.f

|              ‘– codes

|           |                 ‘– fpu.v

|               |– test_fpu

|               |– testbench.v

|                ‘– testcases/

|                               ‘– generate.cpp

‘– CPU                                                                                         // Part 3

|– cpu.f

‘– codes

|                   |– instruction_memory.v                            <– instruction memory with access latency

|                |– data_memory.v                                        <– data memory with access latency

|                 ‘– cpu.v

|– test_cpu

|– testbench.v

‘– testcases/

|– generate.s

‘– generate.cpp

ALU

The ALU spec is as follows:

SignalI/OWidthFunctionality
i clkInput1Clock signal
i rst nInput1Active low asynchronous reset
i data aInput32Input data A may be signed or unsigned depending on the i inst signal
i data bInput32Input data B may be signed or unsigned depending on the i inst signal
i instInput4Instruction signal representing functions to be performed
i validinput1One clock signal when input data a and b are valid
o dataOutput32Calculation result
o overflowOutput1Overflow signal
o validOutput1Should be one cycle signal when your results are valid

The test environment is as follows:

You are asked to implement the following functions in ALU:

i instFunctionDescription
  
4’d3Signed Maxmax(i data a, i data b) (signed)
4’d4Signed Minmin(i data a, i data b) (signed)
4’d8 
4’d9Unsigned Minmin(i data a, i data b) (unsigned)
4’d10Andi data a & i data b
4’d11Ori data a | i data b
4’d12Xori data a         i data b
4’d13BitFlip~ i data a
4’d14BitReverseBit reverse i data a

More details:

  • We will compare the output data and overflow signal with the provided answers
  • For signed 32-bit integer Add, Sub, Mul, Max, Min
    • Two-input signal functions
    • Overflow signal only needs to be considered when Add, Sub or Mul is performed. For Max and Min, set the output overflow signal to 0.
    • We will not compare the return data with the answer provided when overflow happens
  • For unsigned 32-bit integer Add, Sub, Mul, Max, Min
    • Same criteria as signed operations’
  • Xor, And, Or, BitFlip, and BitReverse
    • Set output overflow signal to 0 when the above functions are performed.
    • Xor, And and Or are two-input signal functions.
    • BitFilp and BitReverse are one-input signal functions, therefore, i data b can be ignored.

FPU(20%)

The FPU spec is as follows:

SignalI/OWidthFunctionality
i clkInput1Clock signal
i rst nInput1Active low asynchronous reset
i data aInput32Single precision floating point a
i data bInput32Single precision floating point b
i instInput1Instruction signal representing functions to be performed
i validinput1One clock signal when input data a and b are valid
o dataOutput32Calculation result
o validOutput1Should be one cycle signal when your results are valid

The test environment is as follows:

You are asked to implement the following functions in ALU:

i instFunctionDescription
1’d0Addi data a + i data b (single precision floating point)
1’d1Muli data a * i data b (single precision floating point)

Floating point:

More details:

  • We will compare the output data with provided answers.
  • Follow IEEE-754 single precision floating point format
  • The inputs will not be denormal numbers, infinites, and NaNs, nor will the calculated result.
  • Simple testcases
  • During the computation, the one with smaller exponent will be shifted, you should keep the precision until rounding. As for rounding mode, we use default rounding to nearest even.

I find this pdf useful to explain the rounding and the GRS bits The testcases may be too easy to worry about the rounding.

You may want to reference the diagram described in class to have better idea implementing FPU.

Grading:

  • There are 10 test cases for add and mul. Overall, there are 20 test cases.
  • 0% for each test case

CPU

In this section, you are asked to implement a CPU that supports basic RV64I (not all of them). The CPU spec is as follows:

SignalI/OWidthFunctionality
i clkInput1Clock signal
i rst nInput1Active low asynchronous reset
i     valid instInput1One cycle signal when the instruction form instruction memory is ready
i    instInput3232-bits instruction from instruction memory
i      d valid dataInput1One cycle signal when the data form data memory is ready (used when ld happens)
i d dataInput6464-bits data from data memory (used when ld happens)
o i valid addrOutput1One cycle signal when the pc-address is ready to be sent to instruction memory (fetch the instruction)
o i addrOutput6464-bits address to instruction memory (fetch the instruction)
o d dataOutput6464-bits data to data memory (used when sd happens)
o d addrOutput6464-bits address to data memory (used when ld or sd happens)
o d MemReadOutput1One cycle siganl telling data memory that the current mode is reading (used when ld happens)
o d MemWriteOutput1One cycle siganl telling data memory that the current mode is writing (used when sd happens)
o finishOutput1Stop signal when EOF happens

The provided instruction memory is as follows:

SignalI/OWidthFunctionality
i clkInput1Clock signal
i rst nInput1Active low asynchronous reset
i validInput1Signal that tells pc-address from cpu is ready
i addrInput6464-bits address from cpu
o validOutput1Valid when instruction is ready
o instOutput3232-bits instruction to cpu

And the provided data memory is as follows:

SignalI/OWidthFunctionality
i clkInput1Clock signal
i rst nInput1Active low asynchronous reset
i dataInput6464-bits data that will be stored (used when sd happens)
i addrInput64Write to or read from target 64-bits address (used when ld or sd happens)
i MemReadInput1One cycle signal and set current mode to reading
i MemWriteInput1One cycle signal and set current mode to writing
o validOutput1One cycle signal telling data is ready (used when ld happens)
o dataOutput6464-bits data from data memory (used when ld happens)

The test environment is as follows:

We will only test the instructions highlighted in the red box, as the figures below

And one more instruction to be implemented is

i instFunctionDescription
32’b11111111111111111111111111111111StopStop and set o finish to 1

More details:

  • The instruction_memory.v, data_memory.v and testbench.v files should not be modified
  • We will compare the mem[1024] in data_memory.v result with provided answers to check for correctness
  • There are 1024 bytes memory in data memory module and 16×32 bits memory for instruction memory. No invalid access to instruction or data memory will be involved in the testcases. Hence, there is no need to handle these issues.
  • All the arithmetic operations here are unsigned, including A + B and A + imm. And there is no need to deal with overflow here.
  • You may notice that there’s latency when we want to access the memory
    • For instruction memory, when i_valid is set, the instruction memory will stall for 5 cycles, and then return the instruction to cpu
    • For data memory, when i_MemRead or i_MemWrite is set, the data memory will stall for 7 cycles in both cases, and then return the data to cpu or write the data to memory
    • The latency comes from freezing the module for certain amount of cycles, as shows below

You may want to reference the block diagram of cpu from slides or textbook to have better idea implementing cpu. Notice that the diagram provided here is single cycle cpu, while in this homework, there’s additional latency accessing memory that needs to be considered.

Grading:

  • There are 8 testcases. 5% each. (eof, store, load, add, sub, and, or, xor, andi, ori, xori, slli, srli, bne, beq)

Report (20%)

Write a report about how you implement ALU, FPU, and CPU (maybe some block diagrams).

Submission

  • Zip and upload your file to ceiba in the following format:

r09922028                                                <– zip this folder

|– ALU

|              |– codes/

|           |                         ‘– *.v <– files you used

|                ‘– alu.f                                 <– list all the files needed

|– FPU

|              |– codes/

|           |                         ‘– *.v <– files you used

|               ‘– fpu.f                                <– list all the files needed

|– CPU

|              |– codes/

|           |                         ‘– *.v <– files you used

|               ‘– cpu.f                                <– list all the files needed

‘– report.pdf

  • Late submission within one-week: (Total score)*0.8
  • Late submission within two-week: (Total score)*0.6
  • Late submission over two-week: (Total score)*0
  • If there’s any question, please send email to [email protected]
  • TA hour for this homework:
    • 3:00 5:00 p.m
    • 3:00 5:00 p.m