In this project, registers and register files will be designed and implemented. It has 4 parts. Design each part as a library unit, so that it can be reused in other parts. You can use any available combinational/sequential logisim units in your projects.
(Part-1) Design 2 different types of registers: (1) 8-bit register and (2) 16-bit register.
(Part-1a) The 8-bit register has 4 functionalities that are controlled by 2-bit control signals (FunSel) and an enable input (E).
The block diagram of the 8-bit register and the function table is shown in Figure 1. Symbol 𝜙 means don’t care. Build the register as a library in logisim software so that you can use them in other parts.
| 0 | ɸ | Q | (Retain Value) |
| 1
1 1 1 |
00
01 10 11 |
Q-1
Q+1 I 0 |
(Decrement)
(Increment) (Load) (Clear) |
I E FunSel Q+
E FunSel Q
Figure 1: Block Diagram of the registers (Left) and the function table (Right)
(Part-1b) Design an 16-bit IR register whose block diagram and function table are given in Figure 2.
This register can store 16 bit binary data. However, the input of this register file is only 8 bits. Hence, using the 8 bit input you can load either the lower (bits 7-0) or higher (bits 15-8) half. This is determined by 𝑳/𝑯 signal.
Figure 2: Graphic symbol of the IR register (Left) and its characteristic table (Right)
(Part-2) Design a register file (a structure that contains many registers) that works as follows.
(Part-2a) Design the system shown in Figure 3 which consists of four 8-bit general purpose registers: R1, R2, R3, and R4 and four 8-bit temporary registers: T1, T2, T3, and T4. The details of inputs and outputs are as follows.
Figure 3: 8-bit general purpose and temporary registers, inputs, and outputs
OutASel and OutBSel are used to feed output lines OutA and OutB, respectively. 8 bits of the selected registers are output to OutA and OutB. Figure 4 shows selection of output registers based on the OutASel and OutBSel control inputs.
OutASel OutA OutBSel OutB
| R1 000 R2 001
R3 010 R4 011 |
| T1 100
T2 101 T3 110 T4 111 |
000R1
001R2
010R3
011R4
100T1
101T2
110T3
111T4
Figure 4: OutASel and OutBSel controls
RegSel and TmpSel are 4-bit signals that select the registers to apply the function that is determined by the 2-bit FunSel (Figure 5) signal. The selectes register by Regsel and TmpSel are shown in Figure 6 and Figure 7, respectively.
+
| FunSel | Rx | |
| 00 01
10 11 |
Rx-1
Rx+1 I 0 |
(Decrement)
(Increment) (Load) (Clear) |
Figure 5: FunSel Control Input
RegSel Enabled General Purpose Registers
0000 ALL general purpose registers are enabled (Function selected by FunSel will be applied to R1, R2, R3 and R4)
0001 R1, R2 and R3 are enabled (Function selected by FunSel will be applied to R1, R2 and R3)
0010 R1, R2 and R4 are enabled, Function selected by FunSel will be applied to R1, R2 and R4
0011 R1 and R2 are enabled (Function selected by FunSel will be applied to R1 and R2)
0100 R1, R3 and R4 are enabled (Function selected by FunSel will be applied to R1, R3 and R4)
0101 R1 and R3 are enabled (Function selected by FunSel will be applied to R1 and R3)
0110 R1 and R4 are enabled (Function selected by FunSel will be applied to R1 and R4)
0111 Only R1 is enabled (Function selected by FunSel will be applied to R1)
- R2, R3 and R4 are enabled (Function selected by FunSel will be applied to R2, R3 and R4)
- R2 and R3 are enabled (Function selected by FunSel will be applied to R2 and R3)
- R2 and R4 are enabled (Function selected by FunSel will be applied to R2 and R4)
- Only R2 is enabled (Function selected by FunSel will be applied to R2)
- R3 and R4 are enabled (Function selected by FunSel will be applied to R3 and R4)
- Only R3 is enabled (Function selected by FunSel will be applied to R3)
- Only R4 is enabled (Function selected by FunSel will be applied to R4)
- N0 general purpose register is enabled (All R1, R2, R3 and R4 registers retain their values) Figure 6: RegSel Control Input
TmpSel Enabled Temporary Registers
0000 ALL temporary registers are enabled (Function selected by FunSel will be applied to T1, T2, T3 and T4)
0001 T1, T2 and T3 are enabled (Function selected by FunSel will be applied to T1, T2 and T3)
0010 T1, T2 and T4 are enabled, Function selected by FunSel will be applied to T1, T2 and T4
0011 T1 and T2 are enabled (Function selected by FunSel will be applied to T1 and T2)
0100 T1, T3 and T4 are enabled (Function selected by FunSel will be applied to T1, T3 and T4)
0101 T1 and T3 are enabled (Function selected by FunSel will be applied to T1 and T3)
0110 T1 and T4 are enabled (Function selected by FunSel will be applied to T1 and T4)
0111 Only T1 is enabled (Function selected by FunSel will be applied to T1)
- T2, T3 and T4 are enabled (Function selected by FunSel will be applied to T2, T3 and T4)
- T2 and T3 are enabled (Function selected by FunSel will be applied to T2 and T3)
- T2 and T4 are enabled (Function selected by FunSel will be applied to T2 and T4)
- Only T2 is enabled (Function selected by FunSel will be applied to T2)
- T3 and T4 are enabled (Function selected by FunSel will be applied to T3 and T4)
- Only T3 is enabled (Function selected by FunSel will be applied to T3)
- Only T4 is enabled (Function selected by FunSel will be applied to T4)
- N0 temporary register is enabled (All T1, T2, T3 and T4 registers retain their values)
Figure 7: TmpSel Control Input
For example: If RegSel is 1001, TmpSel is 1111, and FunSel is 01, then the registers R2 and R3 will be incremented with next clock cycle. R1 and R4 will not be affected since they are not enabled by RegSel. Similarly, temporary registers T1, T2, T3, T4 will not be affected since they are not enabled by TmpSel.
(Part-2b) Design the address register file (ARF) system shown in Figure 8 which consists of three 8-bit address registers: program counter (PC), address register (AR), and stack pointer (SP). FunSel and Regsel works as in Part-2a.
Figure 8: 8-bit address registers, inputs, and outputs
OutCSel and OutDSel are used to feed output lines OutC and OutD, respectively. 8 bits of the selected registers are output to OutC and OutD. Figure 9 shows selection of output registers based on the OutCSel and OutDSel control inputs.
Figure 9: OutCSel and OutDSel controls
(Part-3) Design an Arithmetic Logic Unit (ALU) that has two 8-bit inputs, an 8-bit output, and a
4-bit output for zero, negative, carry, and overflow flags. The ALU is shown on the left side of Figure 10. The ALU functions and the flags that will be updated (i.e., – means that the flag will not be affected and √ means that the flag changes based on the OutALU) are given on the right side of Figure 10:
- FunSel selects the function of the ALU.
- OutALU shows the result of the operation that is selected by FunSel and applied on A and/or B inputs.
- Arithmetic operations are done using 2’s complement
- Z (zero) bit is set if OutALU is zero (e.g., when NOT B is zero).
- C (carry) bit is set if OutALU sets the carry (e.g., when LSL A produces carry).
- N (negative) bit is set if the ALU operation generates a negative result (e.g., when A–B results in a negative number).
- O (overflow) bit is set if an overflow occurs (e.g., when A+B results in an overflow).
- Note that Z|C|N|O flags are stored in a register!
|
Figure 10: The ALU (Left) and its characteristic table (Right)
(Circular | Arithmetic | Logical) Shift (Left | Right) operations are depicted in Figure 11, Figure 12, and Figure 13.
Figure 11: Circular Shift Operations
Figure 12: Logical Shift Operations
Figure 13: Arithmetic Shift Operations
(Part-4) Implement the organization in Figure 14. Please note that, the whole system uses the same single clock.
Figure 14: ALU System
